Patents by Inventor Jun Lin

Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250256673
    Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to receive radar data from an ultrawideband radar in a passenger compartment of a vehicle, determine a starting-time for a time-window based on a second derivative of the radar data, identify a motion inside the passenger compartment based on the radar data received during the time-window, and actuate a component of the vehicle based on the identification of the motion.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 14, 2025
    Applicant: Ford Global Technologies, LLC
    Inventors: Jialiang Le, Jun Lin, Ali Hassani, Vivekanandh Elangovan, Collin Hurley
  • Patent number: 12381096
    Abstract: An etching method for selectively etching a material containing Si and O is provided. The etching method includes providing a substrate containing the material containing Si and O in a chamber, repeating a first period for supplying a basic gas, which is started first, and a second period for supplying a fluorine-containing gas, which is started next, with at least a part of the second period not overlapping with the first period, and heating and removing a reaction product generated by the supply of the basic gas and the supply of the fluorine-containing gas.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: August 5, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Yoshiki Igarashi, Satoru Kikushima, Takayuki Suga, Jun Lin, Chengya Chu
  • Publication number: 20250248048
    Abstract: An embedded memory device includes a substrate having an embedded memory region thereon; a first dielectric layer disposed on the substrate within the embedded memory region; conductive vias embedded in the first dielectric layer; data storage structures respectively disposed on the conductive vias; and spacers respectively surrounding the data storage structures over the first dielectric layer. An outer surface of the spacers and a top surface of the first dielectric layer between the spacers constitute a recessed region. A metal-insulator-metal (MIM) capacitor structure is disposed within the recessed region.
    Type: Application
    Filed: March 3, 2024
    Publication date: July 31, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250242195
    Abstract: A rehabilitation pedal structure for a hospital bed includes a footboard, a bottom plate pivotally mounted on two sides of the footboard, and two pedals elastically and pivotally mounted on the bottom plate. The footboard is provided with a slot. The bottom plate is pivotally mounted in the slot. The two pedals can be received in the slot. Each of the pedals is electrically connected with one of two monitors, a counter, and a microcontroller. The counter performs a counting action. When the two pedals are respectively stepped or pressed by a user's two feet or hands, the two pedals swing relative to the bottom plate respectively, and the two monitors indicate a swinging number of the two pedals respectively, to facilitate detection of exercise capacity and rehabilitation times of the user's two feet or hands.
    Type: Application
    Filed: December 6, 2024
    Publication date: July 31, 2025
    Inventors: Chiung-Mei Liu, Yu-Xuan Lin, Ru-Jun Lin, Wan-Hsuan Lin, Ya-Ping Xu, Pei-Yu Chang, Ying-Chien Cheng
  • Publication number: 20250246228
    Abstract: A memory device is provided. The memory device includes multiple first memory arrays, a first write word line driver, and multiple first read word line drivers. Each of the first read word line drivers is coupled to one array in the first memory arrays. A selected one in the first read word line drivers generates a first word line voltage to a corresponding array in the first memory arrays in a first read operation. A first write word line driver is coupled to at least two drivers in the first read word line drivers, and generates a second word line voltage to the first memory arrays in a first write operation. The second word line voltage is greater than the first word line voltage.
    Type: Application
    Filed: January 25, 2024
    Publication date: July 31, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Chung-Cheng CHOU, Pei-Ling TSENG
  • Patent number: 12376323
    Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Chang, Da-Jun Lin, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20250230090
    Abstract: Laminated glass is provided. The laminated glass includes outer glass, an intermediate layer, and inner glass. The intermediate layer is located between the outer glass and the inner glass. A composition of the outer glass and a composition of the inner glass both include total iron expressed as Fe2O3. A mass percentage content of the total iron in the outer glass is Wouter based on a mass of the outer glass, a mass percentage content of the total iron in the inner glass is Winnerbased on a mass of the inner glass, and Wouter and Winner satisfy: 10%>Wouter*Touter+Winner*Tinner>4%. Touter is a thickness of the outer glass in a unit of mm, and Tinner is a thickness of the inner glass in a unit of mm.
    Type: Application
    Filed: April 1, 2025
    Publication date: July 17, 2025
    Applicant: FUYAO GLASS INDUSTRY GROUP CO., LTD.
    Inventors: Jun LIN, Zhe WANG, Li WANG
  • Publication number: 20250226261
    Abstract: A method of manufacturing a gallium nitride device with field plate structure, including forming a passivation layer covering a substrate and a gate, forming recesses in the passivation layer to define a source region and a drain region, forming a source and a drain on the passivation layer, forming a first ILD layer, a stop layer and a second ILD layer sequentially on the source, the drain and the passivation layer, patterning the first ILD layer, the stop layer and the second ILD layer to form dual-damascene recesses, and filling metal in the dual-damascene recesses to form dual-damascene interconnects connecting respectively with the source and the drain.
    Type: Application
    Filed: March 24, 2025
    Publication date: July 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai, Chung-Yi Chiu
  • Publication number: 20250212424
    Abstract: A semiconductor structure with an MIM capacitor includes a first transistor. The first transistor includes a source and a drain. An interlayer dielectric layer covers the first transistor. A source plug penetrates the interlayer dielectric layer and contacts the source. A drain plug penetrates the interlayer dielectric layer and contacts the drain. A metal interlayer dielectric layer covers the interlayer dielectric layer. An MIM capacitor is disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Chung-Yi Chiu
  • Publication number: 20250204661
    Abstract: A carry case for an electronics-enabled eyewear device, such as smart glasses, has charging contacts that are movable relative to a storage chamber in which the eyewear device is receivable. The charging contacts are connected to a battery carried by the case for charging the eyewear device via contact coupling of the charging contacts to corresponding contact formations on an exterior of the eyewear device. The charging contacts are in some instances mounted on respective flexible walls defining opposite extremities of the storage chamber. The contact formations on the eyewear device are in some instances provided by hinge assemblies that couple respective temples to a frame of the eyewear device.
    Type: Application
    Filed: March 13, 2025
    Publication date: June 26, 2025
    Inventors: Jinwoo Kim, Jun Lin
  • Publication number: 20250208641
    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
    Type: Application
    Filed: March 10, 2025
    Publication date: June 26, 2025
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
  • Publication number: 20250212426
    Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Ya-Yin Hsiao, Po-Ching Su, Yi-Fan Li, Kuan-Jhih Hou, Yu-Fu Wang, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Publication number: 20250201731
    Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress tuning structure and a first bonding structure. The stress tuning structure is disposed on the first substrate. The stress tuning structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The first bonding structure is disposed on the stress tuning structure. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate. The second bonding structure is bonded with the first bonding structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-An Shih, Che-Wei Tsai, Da-Jun Lin, I-Ming Tseng, Chung-Sung Chiang, Yu-Chun Chen, Yu-Ping Wang
  • Publication number: 20250204266
    Abstract: A semiconductor device includes a substrate, magnetic tunnel junction (MTJ) structures, and a write structure. The MTJ structures are disposed above the substrate. The write structure is disposed on and connected with the MTJ structures. The write structure includes spin-orbit torque (SOT) patterns and an electrically conductive layer. The SOT patterns are separated from one another, and each of the SOT patterns is disposed on and connected with one of the MTJ structures. The conductive layer covers the SOT patterns. The electrically conductive layer is partly disposed above the SOT patterns in a vertical direction and partly disposed between the SOT patterns in a first horizontal direction.
    Type: Application
    Filed: January 16, 2024
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Chung-Yi Chiu, Bin-Siang Tsai, Fu-Yu Tsai
  • Publication number: 20250196960
    Abstract: The present invention relates to a bicycle with a central controlling computer including a lock.
    Type: Application
    Filed: March 20, 2023
    Publication date: June 19, 2025
    Inventors: Thijs Faber, Zhan Jun Lin, Mykola Zaitsev, Yu-Lun Chao, David Alexander Enthoven, Olivier Hébert, Ahmet Serhan Kuscuoglu, Chien-Cheng Kung
  • Publication number: 20250190306
    Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
  • Patent number: 12329037
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.
    Type: Grant
    Filed: December 12, 2021
    Date of Patent: June 10, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Chau-Chung Hou, Da-Jun Lin, Wei-Xin Gao, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250183151
    Abstract: An MIM capacitor disposed in a modified dual damascene structure includes a dielectric layer, and a first modified dual damascene structure is disposed in the dielectric layer. The first modified dual damascene structure includes a trench and a hole, and the hole connects to the trench. The hole includes a funnel profile. An MIM capacitor is disposed in the first modified dual damascene structure and a first copper layer is disposed in the first modified dual damascene structure and is located on the MIM capacitor.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 5, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun LIN, Fu-Yu Tsai, Bin-Siang Tsai
  • Patent number: 12320511
    Abstract: The disclosure discloses A lamp power adapter, comprising an input conductive component, a shell, a circuit board an end cover and a connecting base for connecting load; one end of the input conductive component is located in the shell, the input conductive componentis integrally fixed with the shell, the other end of the input conductive component is exposed outside the shell, an input connecting terminal, a control circuit and an output connecting terminal are arranged on the circuit board, at least a part of the circuit board is located in the shell, the input connecting terminalis electrically connected to one end of the input conductive component, the connecting base is arranged on the end cover, an output conductive component is arranged on the connecting base, when the end cover fits with the shell, the output conductive component is in plugging fit with the output connecting terminal.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: June 3, 2025
    Assignee: Changzhou Jutai Electronics Co., Ltd.
    Inventors: Jun Lin, Chengqian Pan, Wei Huang, Jin Chen
  • Patent number: 12323710
    Abstract: A head-mounted display device and a control method for an eye-tracking operation are provided. The head-mounted display device includes a frame, a track, a sensor and a controller. The track is disposed on a peripheral region of the frame. The sensor is disposed on the track, and is configured to capture a target image of a target area. The controller is coupled to the sensor, is configured to generate a control signal according to the target image, and adjust a position of the sensor on the peripheral region by moving the sensor according to the control signal.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 3, 2025
    Assignee: HTC Corporation
    Inventors: Yan-Min Kuo, Jun-Lin Guo, Wei-Chen Chen, Chih-Lin Chang, Wei-Cheng Hsu, Cheng-Yu Chen