Abstract: Provided is a process for manufacturing a graphene material, the process comprising (a) injecting a rust stock into a first end of a continuous reactor having a toroidal vortex flow, wherein the first stock comprises graphite and a non-oxidizing liquid (or, alternatively, graphite, an acid, and an optional oxidizer) and the continuous flow reactor is configured to produce the toroidal vortex flow, enabling the formation of a reaction product suspension or slurry at the second end, downstream from the first end, of the continuous reactor; and (b) introducing the reaction product suspension/slurry from the second end back to enter the continuous reactor at or near the first end, allowing the reaction product suspension/slurry to form a toroidal vortex flow and move down to or near the second end to produce a graphene suspension or graphene oxide slurry. The process may further comprise repeating step (b) for at least one time.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A carry case for an electronics-enabled eyewear device, such as smart glasses, has charging contacts that are movable relative to a storage chamber in which the eyewear device is receivable. The charging contacts are connected to a battery carried by the case for charging the eyewear device via contact coupling of the charging contacts to corresponding contact formations on an exterior of the eyewear device. The charging contacts are in some instances mounted on respective flexible walls defining opposite extremities of the storage chamber. The contact formations on the eyewear device are in some instances provided by hinge assemblies that couple respective temples to a frame of the eyewear device.

Abstract: A circular polarizer detection device for detecting a circular polarizer-to-be-detected including a first linear polarizer and a first wave plate is provided. The first linear polarizer has a first transmission axis, the first wave plate has a first fast axis, and there are a preset angle and an error angle between the first transmission axis and the first fast axis. The circular polarizer detection device includes a light source system, a second wave plate and an optical phase demodulation system. A first beam provided by the light source system is converted into a beam-to-be-detected through the circular polarizer-to-be-detected. The beam-to-be-detected enters the rotating second wave plate and then is converted into a second beam. The optical phase demodulation system receives the second beam, generates a phase difference curve, and analyzes a relationship between the rotation angle and the error angle. A circular polarizer detection method is also provided.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: A semiconductor device and a method of fabricating the same, includes at least one dielectric layer, a conductive structure, and a first insulator. The at least one dielectric layer includes a stacked structure having a low-k dielectric layer, an etching stop layer, and a conductive layer between the low-k dielectric layer and the etching stop layer. The conductive structure is disposed in the first dielectric layer. The first insulator is disposed between the conductive layer and the conductive structure.

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area.

Abstract: The present disclosure is related to a semiconductor device and a fabricating method thereof, and the semiconductor device includes a first dielectric layer and a first conductive structure. The first dielectric layer includes a stacked structure including a low-k dielectric layer, an etching stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etching stop layer, wherein a carbon concentration within the carbon-rich dielectric layer is above 15%. The first conductive structure is disposed in the first dielectric layer.

Abstract: A joining element and joining method thereof are provided. The joining element comprises a head section, a rib section, and a tip section, wherein each cross section of the tip section has a geometric shape, and the geometric shape is formed by overlapping a plurality of ellipses. When the joining element applies downward pressure and rotational force on an assembly component, an inner concave portion of the geometric shape generates more plastic deformation heat than fraction heat on the material of the joining element. It facilitates the softening of the material in the assembly component, allowing for greater plastic deformation and, in turn, improves the assembly efficiency.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

Abstract: An optically transparent and electrically conductive film composed of metal nanowires or carbon nanotubes combined with pristine graphene with a metal nanowire-to-graphene or carbon nanotube-to-graphene weight ratio from 1/99 to 99/1, wherein the pristine graphene is single-crystalline and contains no oxygen and no hydrogen, and the film exhibits an optical transparence no less than 80% and sheet resistance no higher than 300 ohm/square. This film can be used as a transparent conductive electrode in an electro-optic device, such as a photovoltaic or solar cell, light-emitting diode, photo-detector, touch screen, electro-wetting display, liquid crystal display, plasma display, LED display, a TV screen, a computer screen, or a mobile phone screen.

Abstract: A integrated circuit (IC) chip includes a dielectric layer and a first conductive pillar disposed in the dielectric layer. The first conductive pillar runs through the dielectric layer in a thickness direction of the dielectric layer. The chip further includes a first conductive pattern and a second conductive pattern that are located on two opposite sides of the first conductive pillar and are coupled to the first conductive pillar. The first conductive pillar includes a metal pillar and a metal compound layer. The metal compound layer is located between the metal pillar and the dielectric layer and covers a part of a side surface of the metal pillar. The first conductive pillar is directly in contact with the dielectric layer, and no barrier layer is disposed between the first conductive pillar and the dielectric layer.

Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.

Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

Abstract: An antenna system comprises a driven antenna element connected to a printed circuit board (PCB), and a plurality of PCB extenders provided by electrical conductors connected to a PCB ground plane for cooperation with the driven antenna element in signal communication. In an eyewear device that incorporates the antenna system, the plurality of PCB extenders are provided by conductive structural elements incorporated in an eyewear frame.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.