Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.

Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

Abstract: A integrated circuit (IC) chip includes a dielectric layer and a first conductive pillar disposed in the dielectric layer. The first conductive pillar runs through the dielectric layer in a thickness direction of the dielectric layer. The chip further includes a first conductive pattern and a second conductive pattern that are located on two opposite sides of the first conductive pillar and are coupled to the first conductive pillar. The first conductive pillar includes a metal pillar and a metal compound layer. The metal compound layer is located between the metal pillar and the dielectric layer and covers a part of a side surface of the metal pillar. The first conductive pillar is directly in contact with the dielectric layer, and no barrier layer is disposed between the first conductive pillar and the dielectric layer.

Abstract: An antenna system comprises a driven antenna element connected to a printed circuit board (PCB), and a plurality of PCB extenders provided by electrical conductors connected to a PCB ground plane for cooperation with the driven antenna element in signal communication. In an eyewear device that incorporates the antenna system, the plurality of PCB extenders are provided by conductive structural elements incorporated in an eyewear frame.

Abstract: This application describes systems and methods for assaying micro-objects in a microfluidic device. These methods include contacting a reagent with a micro-object by introducing a reagent in a first fluidic medium to a flow region of a microfluidic device, wherein the microfluidic device comprises the flow region and a chamber comprising a proximal opening fluidically connecting the chamber to the flow region, diffusing the reagent from the flow region into the chamber; introducing a micro-object into the flow region of the microfluidic device, and diffusing the reagent from the chamber to the flow region to contact the reagent with the micro-object within the flow region. Other embodiments are described.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

Abstract: A hinge assembly mounted on a housing of form part of an electronic device includes a metal hinge base extending through a mounting hole in a wall of the housing, the hinge base being connected in heat transfer relationship to a metal anchor plate on an inner side of the housing wall. The anchor plate additionally serves as a mounting base for heat-generating electronics inside the housing, the heat-generating electronics being in heat transfer relationship with the anchor plate, so that the anchor plate and the hinge base together form part of a heat transfer path conducting heat from the interior of the housing to an exterior heatsink provided be and external device component.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A positive resist composition is provided comprising (A) an acid generator in the form of a sulfonium salt consisting of a fluorine-containing sulfonate anion and a fluorine-containing sulfonium cation, (B) a quencher in the form of a sulfonium salt containing at least two fluorine atoms in its cation or containing at least 5 fluorine atoms in its anion and cation, and (C) a base polymer comprising repeat units (a1) having a carboxy group whose hydrogen is substituted by an acid labile group and/or repeat units (a2) having a phenolic hydroxy group whose hydrogen is substituted by an acid labile group. The resist composition exhibits a high sensitivity, high resolution and improved LWR or CDU.

Abstract: This application discloses an Ethernet coding method and apparatus, to adapt to a scenario in which a higher transmission bit error rate is caused by a high bandwidth. The method includes: a transmit end encodes first to-be-encoded information by using a first forward error correction (FEC) codeword, to obtain first encoded data, where the first forward error correction FEC codeword is a Reed-Solomon forward error correction (RS-FEC) codeword; and the transmit end encodes the first encoded data by using a second FEC codeword, to obtain second encoded data, where a code length N and an information bit length K of the second FEC codeword satisfy the following formula: M1*N/K?M2, where M1 is a throughput of the first encoded data, and M2 is a throughput of the second encoded data.

Abstract: In one aspect, a laminated glass includes first and second glass plates and at least two connectors, with the thickness of the second glass plate being not larger than 1.6 mm and a middle layer being arranged between the first glass plate and the second glass plate. Each connector comprises an embedded part. The embedded part is arranged between the middle layer and the second glass plate, so as to be in contact with the middle layer and the second glass plate at the same time. The laminated glass has a clinging value A=T1×T2×L/(T3)3, and the clinging value A is at least 20, wherein the thickness of the second glass plate is T1, the thickness of the intermediate layer is T2, the thickness of the embedded part is T3, and the distance between the embedded parts of two adjacent connectors is L.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: Head-up display glass and a head-up display system are provided. The head-up display glass includes laminated glass and a reflective coating. The laminated glass includes outer glass, a polymer interlayer, and inner glass. The reflective coating includes an inner barrier layer, an improvement layer, and at least one laminated structure that are stacked. The at least one laminated structure each includes a high refractive-index layer and a low refractive-index layer that are stacked in sequence in a direction away from the inner barrier layer. The high refractive-index layer has a refractive index greater than or equal to 1.8. The low refractive-index layer has a refractive index less than 1.7. The improvement layer is disposed between the inner barrier layer and the at least one laminated structure, or between the high refractive-index layer and the low refractive-index layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: Apparatuses and systems for wearable devices such as eyewear are described. According to one embodiment, the wearable device includes a frame, a temple, onboard electronics components, and a coupling mechanism. The frame is configured to hold one or more optical elements. The temple is connected to the frame at an articulated joint such that the temple is disposable between a collapsed condition and a wearable condition in which the device is wearable by a user to hold the one or more optical elements within user view. The onboard electronics components comprise at least a pair of electronics components carried by the frame and the temple respectively. The coupling mechanism is incorporated in the articulated joint and that is configured to electrically connect the pair of electronics components across the articulated joint both when the temple is in the wearable condition and when the temple is in the collapsed condition.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: Various waveguides and image display systems are disclosed herein. In an example, an image display system can include an optical engine configured to generate an image and a waveguide. The waveguide can have a light in-coupling region formed along a peripheral edge of the waveguide, the light in-coupling region including a first surface with a first set of diffraction gratings, and a light exit region formed along a top surface of the waveguide, the light exit region including a second set of diffraction gratings. The first set of diffraction gratings can be configured to diffract light towards the second set of diffraction gratings, and the second set of diffraction gratings can be configured to diffract light towards the user's eye.