Patents by Inventor Jun Lin

Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESISTIVE MEMORY WITH LOW VOLTAGE OPERATION
    Publication number: 20240355389
    Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih
  • Semiconductor device and method for fabricating the same
    Patent number: 12127414
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: October 22, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
  • SUNROOF GLASS AND VEHICLE
    Publication number: 20240343638
    Abstract: Sunroof glass and vehicle are provided. The sunroof glass includes a glass substrate, a metal absorption layer, and an anti-reflective layer. The glass substrate has an outer surface and an inner surface. The metal absorption layer and the anti-reflective layer are sequentially stacked on the inner surface in a direction away from the glass substrate. The anti-reflective layer includes at least one stacking including a high refractive-index layer and a low refractive-index layer. The high refractive-index layer has a refractive index greater than or equal to 1.7. The low refractive-index layer has a refractive index less than 1.7.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: FUJIAN WANDA AUTOMOBILE GLASS INDUSTRY CO., LTD.
    Inventors: Yuemin LU, Jun LIN, Zhixin CHEN
  • COMPOSITION FOR PRESERVATION OF CELLS, TISSUES OR ORGANS, COMPRISING ISOLATED MITOCHONDRIA, AND USE THEREOF
    Publication number: 20240341299
    Abstract: The present invention relates to a preservation solution composition for the preservation of an isolated cell, tissue, or organ, comprising isolated mitochondria; and a method for preserving an isolated cell, tissue, or organ by using the same. The preservation solution composition according to the present invention has excellent long-term preservability while maintaining the activity of isolated cell, tissue, or organ. Therefore, the present invention may be effectively used in the transplantation medicine field for ultimately improving transplant success rates and in the regenerative medicine field and the like.
    Type: Application
    Filed: July 22, 2022
    Publication date: October 17, 2024
    Inventors: Young-Cheol KANG, Kyuboem HAN, Chun-Hyung KIM, Hong Kyu LEE, Soomin KIM, Hendra TANOTO, Yin Hua ZHANG, Zhi Jun LIN, Hui Xing CUI
  • Method for fabricating semiconductor device
    Patent number: 12120962
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: October 15, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • RRAM CIRCUIT AND METHOD
    Publication number: 20240331770
    Abstract: A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
  • SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20240332066
    Abstract: A semiconductor structure includes a substrate; a first dielectric layer on the substrate; an etch stop layer on the first dielectric layer; a second dielectric layer on the etch stop layer; a first conductor and a second conductor in the second dielectric layer, an air gap in the second dielectric layer and between the first conductor and the second conductor; and a low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Chih-Wei Chang, Fu-Yu Tsai, Bin-Siang Tsai
  • Manufacturing method of memory device
    Patent number: 12108691
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: October 1, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chich-Neng Chang, Da-Jun Lin, Shih-Wei Su, Fu-Yu Tsai, Bin-Siang Tsai
  • Work mode indicator and power converter for lamp
    Patent number: 12108505
    Abstract: The present disclosure relates to A work mode indicator for a lamp, including: a user command switch unit configured to issue a switch command to switch a work mode; a controller configured to output a work mode indication control signal, the controller being electrically connected to the user command switch unit; and a work mode indication unit; wherein the work mode indication unit is a multicolor light-emitting indicator lamp configured to emit multiple colors of light to indicate different work modes, and the controller has an output end electrically connected to the multicolor light-emitting indicator lamp. With the present disclosure, different work modes of the lamp may be indicated through a multicolor light-emitting indicator lamp, whereby a user can determine which work mode the lamp is in.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: October 1, 2024
    Assignee: Changzhou Jutai Electronic Co., Ltd.
    Inventors: Jun Lin, Chengqian Pan, Bin Chen
  • Semiconductor device and method for fabricating the same
    Patent number: 12108681
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
  • FIELD-EFFECT TRANSISTOR AND PREPARATION METHOD THEREFOR, AND ELECTRONIC DEVICE
    Publication number: 20240321994
    Abstract: An example of a field-effect transistor includes a source region, a drain region, a plurality of channel regions, and a gate region. The channel region includes a first and second semiconductor layers. A material of the first semiconductor layer includes silicon germanium, and a material of the second semiconductor layer includes germanium. The gate region wraps the plurality of channel regions and fills a gap between the plurality of channel regions. The first semiconductor layer has a top surface and a bottom surface that are perpendicular to a stacking direction of the plurality of channel regions, and a side surface that is parallel to the stacking direction of the plurality of channel regions. The second semiconductor layer is disposed on the top surface, the bottom surface, and the side surface of the first semiconductor layer.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 26, 2024
    Inventor: Jun LIN
  • RESISTIVE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240324474
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE
  • ISOLATION STRUCTURE FOR ISOLATING EPITAXIALLY GROWN SOURCE/DRAIN REGIONS AND METHOD OF FABRICATION THEREOF
    Publication number: 20240313072
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Semiconductor structure
    Patent number: 12089512
    Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: September 10, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Wei Su, Da-Jun Lin, Chih-Wei Chang, Bin-Siang Tsai, Ting-An Chien
  • WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAME
    Publication number: 20240290731
    Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Chin-Chia Yang, Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai
  • Light sensing module and electronic device using the same
    Patent number: 12072236
    Abstract: A light sensing module includes a substrate, a light sensing unit, a first light-transmissive component, and a light shielding layer. The light sensing unit is disposed on the substrate to sense an intensity of a working light beam, and has an upper light receiving surface and a lateral surface perpendicular to the upper light receiving surface. The first light-transmissive component covers the light sensing unit, and has a first refractive index between a refractive index of the light sensing unit and a refractive index of air. The light shielding layer surrounds the lateral surface and is covered by the first light-transmissive component.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: August 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Bo-Jhih Chen, Zi-Jun Lin, Kuo-Ming Chiu, Yung-Chang Jen, Meng-Sung Chou, Chang-Hung Hsieh
  • Magnetic random access memory structure
    Patent number: 12069960
    Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 20, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Ching-Hua Hsu, Fu-Yu Tsai, Bin-Siang Tsai
  • Systems and methods for traffic monitoring
    Patent number: 12067868
    Abstract: The present disclosure may provide a system. The system may obtain at least one pair of images from at least one pair of capture devices. Each of the at least one pair of capture devices may include a first capture device and a second capture device, and each of the at least one pair of images may include a first image captured by the first capture device and a second image captured by the second capture device. The system may determine first identification information of at least one first object in the first image and determine second identification information of at least one second object in the second image. Further, the system may determine at least one information pair by correlating at least a part of the first identification information and at least a part of the second identification information.
    Type: Grant
    Filed: March 6, 2022
    Date of Patent: August 20, 2024
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Jun Lin, Yayun Wang, Wenbo Chen
  • OCCUPANT HEAD POSITION IN VEHICLE
    Publication number: 20240257389
    Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to receive a first image frame from a first camera of a vehicle and a second image frame from a second camera of the vehicle, identify a common point in the first image frame and the second image frame, determine a projected position of the common point projected onto a plane based on the first image frame and the second image frame, and determine a position of the common point based on the projected position. A first optical axis defined by the first camera and a second optical axis defined by the second camera are in the plane.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Applicant: Ford Global Technologies, LLC
    Inventors: Jun Lin, Jialiang Le
  • HYBRID SELF-TRACKING REFERENCE CIRCUIT FOR RRAM CELLS
    Publication number: 20240257870
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng