Patents by Inventor Jun Mo Koo

Jun Mo Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150296450
    Abstract: A wireless communication terminal according to the present invention, if it is found that an access point (AP) is available from searching a wireless communication network, for example, a Wi-Fi network, checks whether the AP is registered in a list of delayed access points. If the access point in included in the list of delayed access points, the wireless communication terminal re-searches the Wi-Fi network after a predetermined waiting time is passed. If the AP is unavailable, connection to a current mobile communication network is maintained whereas, if the AP is still available, the wireless communication terminal switches connection from a mobile communication network to the AP. If not registered in a list of delayed access points, the wireless communication terminal immediately switches connection from a mobile communication network to the AP without the waiting time.
    Type: Application
    Filed: February 14, 2013
    Publication date: October 15, 2015
    Inventors: Jun Mo Koo, Seung Jun Lee, Sang Kug Yi, Soon Uk Kim
  • Patent number: 9142515
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, DaeSik Choi, Jun Mo Koo
  • Patent number: 8999760
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: April 7, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8993377
    Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Jun Mo Koo, Pandi C. Marimuthu, Seung Wook Yoon, Il Kwon Shim
  • Patent number: 8866294
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20140264786
    Abstract: A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.
    Type: Application
    Filed: June 1, 2014
    Publication date: September 18, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20140252631
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 11, 2014
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8796137
    Abstract: A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 5, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20140077344
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, DaeSik Choi, Jun Mo Koo
  • Publication number: 20140077389
    Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 20, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Jun Mo Koo, Pandi C. Marimuthu, Yaojian Lin, See Chian Lim
  • Publication number: 20140054802
    Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.
    Type: Application
    Filed: March 12, 2013
    Publication date: February 27, 2014
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Il Kwon Shim, Jun Mo Koo
  • Patent number: 8642381
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, DaeSik Choi, Jun Mo Koo
  • Publication number: 20130299982
    Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.
    Type: Application
    Filed: July 17, 2013
    Publication date: November 14, 2013
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo, HeeJo Chi
  • Patent number: 8435834
    Abstract: A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: May 7, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Rajendra D. Pendse, Jun Mo Koo
  • Publication number: 20130001771
    Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 3, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20120261818
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 18, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8288201
    Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 16, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20120248596
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Application
    Filed: June 8, 2012
    Publication date: October 4, 2012
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8241964
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: August 14, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8236617
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo