Patents by Inventor Jun Nakajima

Jun Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9855794
    Abstract: The bicycle hub assembly includes a hub axle, a hub body, and a rear-sprocket supporting member. A first axial length is defined between a first axial frame abutment surface of the hub axle and an axially rear-sprocket abutment surface of the rear-sprocket supporting member in the axial direction. The first axial length is smaller than or equal to 38.00 mm. A second axial length is defined between a first axially outer part 70b of the hub body and a second axially outer part 71b of a second spoke-mounting portion 71 of the hub body in the axial direction. The second axial length is larger than or equal to 55.00 mm.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SHIMANO INC.
    Inventors: Jun Nakajima, Kazuki Koshiyama
  • Patent number: 9830178
    Abstract: The present application is directed to dynamic reassignment for multi-OS devices. An example device may comprise equipment, at least two operating systems, a kernel for each OS to provide an interface between the OS and the equipment and a virtual machine manager (VMM). OS selection agents in each OS may interact with a kernel mode controller (KMC) in the VMM. For example, the OS selection agent may transmit a message instructing the KMC to transition the foreground OS to the background and transition a background OS to the foreground. The KMC may transmit signals to the kernels of the foreground and background operating systems causing at least one driver in the foreground OS kernel to save a current equipment state and release control over the equipment while also causing at least one driver in the background OS kernel to restore an equipment state and to take control over the equipment.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 28, 2017
    Assignee: INTEL CORPORATION
    Inventor: Jun Nakajima
  • Patent number: 9781209
    Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Mesut A. Ergin, Jr-Shian Tsai, Janet Tseng, Ren Wang, Jun Nakajima, Tsung-Yuan Tai
  • Patent number: 9760294
    Abstract: A management computer stores, in a memory, virtual logical volume management information showing information on virtual logical volumes provided to a host computer by a storage device, and pool management information showing information related to a use status of pools. The management computer acquires performance information related to an access to the storage device from the host computer, determines whether the acquired performance related to the access satisfies a predetermined first required performance, or not, and specifies any virtual logical volume which is a cause of the state based on the virtual logical volume management information if the first required performance is not satisfied. The management computer calculates a capacity consumption trend of the real area included in each pool based on the pool management information, creates a countermeasure for satisfying the first required performance implementable after a given time, and outputs the countermeasure to an output device.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 12, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Kyoko Miwa, Jun Nakajima, Yukinori Sakashita, Tsukasa Shibayama, Masataka Nagura
  • Patent number: 9751362
    Abstract: A wheel securing axle includes a shaft that includes a first end portion, a second end portion including a thread, and a shaft axis, a washer rotationally supported by the first end portion of the shaft, and a click mechanism arranged between the shaft and the washer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 5, 2017
    Assignee: Shimano Inc.
    Inventors: Jun Nakajima, Kazuki Koshiyama
  • Patent number: 9747156
    Abstract: A management system that generates a plan which is a countermeasure against an event occurring in a computer system includes: a plan generating unit configured to generate a plan according to the event; and an indicator generating unit configured to generate, as a performance change evaluation indicator of the plan, information on a change in performance of a resource of the computer system, which can occur due to other subject's process executed by the other subject different from a subject of the plan when the plan generated by the plan generating unit is executed.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 29, 2017
    Assignee: HITACHI, LTD.
    Inventors: Jun Nakajima, Masataka Nagura, Yukinori Sakashita
  • Patent number: 9747123
    Abstract: Technologies for multi-level virtualization include a computing device having a processor that supports a root virtualization mode and a non-root virtualization mode. A non-root hypervisor determines whether it is executed under control of a root hypervisor, and if so, registers a callback handler and trigger conditions with the root hypervisor. The non-root hypervisor hosts one or more virtual machines. In response to a virtual machine exit, the root hypervisor determines whether a callback handler has been registered for the virtual machine exit reason and, if so, evaluates the trigger conditions associated with the callback handler. If the trigger conditions are satisfied, the root hypervisor invokes the callback handler. The callback handler may update a virtual virtualization support object based on changes made by the root hypervisor to a virtualization support object. The root hypervisor may invoke the callback handler in the non-root virtualization mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Jun Nakajima, Asit K. Mallick, Harshawardhan Vipat, Madhukar Tallam, Manohar R. Castelino
  • Publication number: 20170206177
    Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Jr-Shian Tsai, Ravi L. Sahita, Mesut A. Ergin, Rajesh M. Sankaran, Gilbert Neiger, Jun Nakajima, Edwin Verplanke, Barry E. Huntley, Tsung-Yuan C. Tai
  • Publication number: 20170206027
    Abstract: A management system, which manages at least a computer system including a copy destination VOL, receives first performance related information including information related to a resource related to an operation with which a copy source VOL is associated as an I/O destination, and stores the received first performance related information. When an operation migrates from a first site to a second site (for example, when the first site is affected by a disaster), the management system reallocates a resource of the second site based on both the first performance related information and second performance related information including information related to a resource related to an operation originally executed at the second site among a resource group of the second site.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 20, 2017
    Applicant: HITACHI, LTD.
    Inventors: Jun NAKAJIMA, Hironori EMARU, Yutaka KUDOU
  • Patent number: 9644413
    Abstract: There is provided a seat opening/closing structure for a saddle riding vehicle that suppresses the cost and simplifies the structure to enhance usability. A seat hinge 31 has a vehicle-body-side hinge 51A provided to a vehicle body side, and a seat-side hinge 52 which is turnably secured to the vehicle-body-side hinge 51A through a hinge pin 55. The seat-side hinge 52 has a projecting portion 52h extending to the vehicle-body-side hinge 51A, the vehicle-body-side hinge 51A is provided with a leaf spring 64 having a top portion 64a with which the projecting portion 52h can come into contact, and the projecting portion 52h gets over the top portion 64a of the leaf spring 64 when the seat is opened, whereby the seat-side hinge 52 is supported by the leaf spring 64 and the seat is kept under an open state.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: May 9, 2017
    Assignee: Honda Motor Co., Ltd.
    Inventors: Naoki Hara, Junji Kikuno, Jun Nakajima, Makoto Takitani
  • Patent number: 9626129
    Abstract: A computer system is provided which includes a host computer having a volume, a storage apparatus including a storage media, the storage apparatus providing a RAID group configured by the storage media, a logical volume configured by the RAID group, a pool configured by the logical volume, and a virtual volume allocated from the pool and corresponding to the volume of the host computer. The computer system also includes a management server to store performance information regarding the logical volume and/or RAID group and mapping information regarding a relationship among components of the computer system in view of logical and physical connections. The management server determines whether a correspondence relationship exists among the components by referring to the performance information, and outputs a relationship among the components based on the determination of the correspondence relationship and the mapping information.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 18, 2017
    Assignee: HITACHI, LTD.
    Inventors: Jun Nakajima, Daisuke Shinohara
  • Patent number: 9619314
    Abstract: A management system manages a plurality of management target devices. A storage device stores one or more rules, plan information, and plan history information. A control device specifies a first cause event that is a candidate of a cause of the event that has occurred in any one of the management target devices based on the one or more rules, specifies a plurality of first plans that can be executed in the case in which the first cause event is a cause based on the plan information, calculates an index value indicating a possibility of succeeding in a failure recovery in the case in which the plan is executed for each of the plurality of first plans based on the plan history information, and displays data indicating any one or more plans of the plurality of first plans according to a display mode decided based on the index value.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 11, 2017
    Assignee: HITACHI, LTD.
    Inventors: Masataka Nagura, Jun Nakajima, Takayuki Nagai, Yutaka Kudo
  • Publication number: 20170090963
    Abstract: Technologies for multi-level virtualization include a computing device having a processor that supports a root virtualization mode and a non-root virtualization mode. A non-root hypervisor determines whether it is executed under control of a root hypervisor, and if so, registers a callback handler and trigger conditions with the root hypervisor. The non-root hypervisor hosts one or more virtual machines. In response to a virtual machine exit, the root hypervisor determines whether a callback handler has been registered for the virtual machine exit reason and, if so, evaluates the trigger conditions associated with the callback handler. If the trigger conditions are satisfied, the root hypervisor invokes the callback handler. The callback handler may update a virtual virtualization support object based on changes made by the root hypervisor to a virtualization support object. The root hypervisor may invoke the callback handler in the non-root virtualization mode. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Jun Nakajima, Asit K. Mallick, Harshawardhan Vipat, Madhukar Tallam, Manohar R. Castelino
  • Publication number: 20170054659
    Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Applicant: Intel Corporation
    Inventors: MESUT A. ERGIN, JR-SHIAN TSAI, JANET TSENG, REN WANG, JUN NAKAJIMA, TSUNG-YUAN TAI
  • Publication number: 20170036728
    Abstract: A wheel-securing axle secures a wheel to a bicycle body. The axle has a shaft and a one-way clutch mechanism. The axle includes a shaft that has a threaded section and a rotational center axis. The one-way clutch mechanism includes a lock member for contacting the bicycle body. The one-way clutch mechanism permits relative rotation between the lock member and the shaft in a first direction about the rotational center axis and limits relative rotation between the lock member and the shaft in a second direction. The lock member limits relative rotation between the shaft and the bicycle body in the first direction when the lock member contacts the bicycle body.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventor: Jun NAKAJIMA
  • Publication number: 20170036729
    Abstract: A bicycle wheel securing structure is basically provided with an axle member, a head member, a lever member and an adjusting member. The axle member is at least partially hollow, and includes a first end portion, a second end portion and a vehicle body engagement portion. The vehicle body engagement portion is provided to the second end portion for engaging a bicycle frame. The head member is disposed on the first end portion. The lever member is configured to turn the head member around an axis between a first position and a second position. The lever member presses the head member from the first end portion to the second end portion by being turned from the second position to the first position. The adjusting member is provided inside the axle member for adjusting an axial position of the head member.
    Type: Application
    Filed: July 6, 2016
    Publication date: February 9, 2017
    Inventor: Jun NAKAJIMA
  • Patent number: 9517687
    Abstract: A battery unit mounting structure includes a pair of right and left vehicle body frame members extending in a vehicle front-rear direction, a pair of right and left side members extending in the vehicle front-rear direction, a battery unit disposed between the right and left side members, and a reinforcement. The right and left vehicle body frame members are disposed respectively at right and left outer side portions of a vehicle body in a vehicle-width direction. The right and left side members are connected respectively to inner sides of the right and left vehicle body frame members in the vehicle-width direction. The reinforcement is disposed on a bottom or top surface of the battery unit, and disposed at a position at which the reinforcement overlaps with the battery unit in a plan view. The reinforcement extending in the vehicle-width direction is longer than the battery unit in the vehicle-width direction.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 13, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Jun Nakajima
  • Patent number: 9463842
    Abstract: A bicycle wheel securing structure is provided with a shaft member, a head member, a lever member, an adjustment member and a positioning mechanism. The shaft member has a first end portion, a second end portion and an engaging part. The head member is movably disposed on the first end portion. The lever member is movably provided on the head member around a pivot axis that intersects with an axial direction of the shaft member to move the shaft member in the axial direction with respect to the head member. The adjustment member is movably provided on the head member in the axial direction and that can adjust a final fixing position of the lever member. The positioning mechanism is provided between the head member and the adjustment member to selectively maintain a position of the adjustment member in a plurality of axially spaced apart locations.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: October 11, 2016
    Assignee: Shimano Inc.
    Inventors: Jun Nakajima, Kazuki Koshiyama
  • Publication number: 20160290858
    Abstract: A photosensor is provided with a sensor circuit assembly. The sensor circuit assembly includes alight emitter, a light receiver, a light-emitter support, a light-receiver support, and a connecting part. The light emitter and the light receiver face each other. The light-emitter support extends from and supports the light emitter. The light-receiver support extends from and supports the light receiver. The connecting part connects one end of the light-emitter support with one end of the light-receiver support. The connecting part includes a seal and a connection terminal that protrudes from the seal. The connection terminal includes a first press-contact part, and a first pressure part that presses the first press-contact part in a press-contact direction.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 6, 2016
    Applicant: OMRON Corporation
    Inventors: Tsuyoshi MIYATA, Jun NAKAJIMA, Seiji MIYASHITA, Kiyoshi IMAI, Kazuya OHTSUKI
  • Patent number: 9454497
    Abstract: Technologies for secure inter-virtual-machine shared memory communication include a computing device with hardware virtualization support. A virtual machine monitor (VMM) authenticates a view switch component of a target virtual machine. The VMM adds configures a secure memory view to access a shared memory segment. The shared memory segment may include memory pages of a source virtual machine or the VMM. The view switch component switches to the secure memory view without generating a virtual machine exit event, using the hardware virtualization support. The view switch component may switch to the secure memory view by modifying an extended page table (EPT) pointer. The target virtual machine accesses the shared memory segment via the secure memory view. The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Jun Nakajima, Jr-Shian Tsai, Ravi L. Sahita, Mesut A. Ergin, Edwin Verplanke, Rashmin N. Patel, Alexander W. Min, Ren Wang, Tsung-Yuan C. Tai