Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.

Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for using a filter for temporal noise reduction. In some implementations, image data for a series of frames, including a first input frame followed by a second input frame, of a video is obtained. A first output frame resulting from noise reduction processing for the first input frame and a measure of variance associated with a portion of the first output frame is obtained. An interpolation setting for noise reduction processing of a portion of the second input frame is determined. A second output frame is generated by interpolating the portion of the second input frame with the corresponding portion of the first output frame.

Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

Abstract: A shift register includes stages each constituted by a unit circuit provided with thin-film transistors that separate a control node (i.e. a node that controls output from a unit circuit) into an output-side first control node and an input-side second control node. One of the thin-film transistors has a control terminal that is supplied with a set signal that is an output signal from a unit circuit constituting a preceding stage. The other of the thin-film transistors has a control terminal that is supplied with a reset signal that is an output signal from a unit circuit constituting a subsequent stage.

Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

Abstract: The present invention provides a reagent comprising an antibody from which part of CH3 or CH2 in the Fc region is deleted.

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing highlight recovery. One of the methods includes receiving raw image data of an image, the raw image data comprising, for each of a plurality of highlight regions in the image, original channel values for one or more channels of the highlight region; processing the raw image data to generate updated image data, wherein the updated image data comprises updated channel values for each highlight region in the image, and wherein, for each of one or more highlight regions of the image, one or more updated channel values of the highlight region exceed a maximum channel value according to a predetermined data precision; and performing a hue correction process on the updated channel values of the one or more highlight regions of the image to generate final channel values that satisfy the predetermined data precision.

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.

Abstract: A display device includes a first display panel with a touch function, a second display panel without a touch function, a first data line drive circuit and a first demultiplexer circuit configured to drive data lines of the first display panel in a time-division manner in accordance with K first control signals, and a second data line drive circuit and a second demultiplexer circuit configured to drive data lines of the second display panel in a time-division manner in accordance with K second control signals. A horizontal period used to drive the first display panel is shorter than a horizontal period used to drive the second display panel, and a length of a period in which each of the first control signals is at a selection level and a length of a period in which each of the second control signals is at a selection level are approximately the same.

Abstract: An image forming apparatus is used in a post-payment system based on a customer's electronic money, and includes an image forming section, a communication section, and a controller. The image forming section performs a printing operation of forming an image on a sheet. The communication section performs communication so as to acquire settlement information including information that identifies the customer. The controller controls the image forming section and the communication section. As to the printing operation performed after acquisition of the settlement information, the controller settles a printing fee with a discount in a unit price per sheet in a situation where a printed sheet count is a predetermined number or more.

Abstract: A display device includes a first display panel with a touch function, a second display panel without a touch function, a first data line drive circuit and a first demultiplexer circuit configured to drive data lines of the first display panel in a time-division manner in accordance with K first control signals, and a second data line drive circuit and a second demultiplexer circuit configured to drive data lines of the second display panel in a time-division manner in accordance with K second control signals. A horizontal period used to drive the first display panel is shorter than a horizontal period used to drive the second display panel, and a length of a period in which each of the first control signals is at a selection level and a length of a period in which each of the second control signals is at a selection level are approximately the same.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion and can switch a shift direction, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion and can switch the shift direction. A first buffer circuit is provided on one side of both ends of each gate bus line, and a second and a third buffer circuits are provided on another side thereof.