Patents by Inventor Jun Nishimura

Jun Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149007
    Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.
    Type: Application
    Filed: October 11, 2024
    Publication date: May 8, 2025
    Inventors: Kengo HARA, Tohru DAITOH, Yoshihito HARA, Jun NISHIMURA, Yohei TAKEUCHI
  • Publication number: 20250137203
    Abstract: There is provided a technology capable of controlling the occurrence of “migration” of a foam material to a contact object. The present technology provides a package material containing: a fibrous material that includes waste paper and/or pulp; a binder; sodium hydrogen carbonate; a surfactant; and a water-soluble softener, the water-soluble softener being a urea derivative having a chemical structural formula of R1,R2—N—CO—N—R3,R4 (R1 to R4 are each H or a saturated and/or unsaturated hydrocarbon group having 1 to 4 carbon atoms) and/or a water-soluble polyhydric alcohol having 3 to 15 carbon atoms, the number of carbon atoms and the number of hydroxyl (OH) groups in a molecular structure of the water-soluble polyhydric alcohol satisfying a relationship of the number of hydroxy groups<the number of carbon atoms.
    Type: Application
    Filed: August 10, 2022
    Publication date: May 1, 2025
    Inventors: Yuuko TABEI, Takashi TSUGAMI, Yasuhito INAGAKI, Jun NISHIMURA, Kazuhiko AIKO, Takayuki YAGI, Mitsuhiro OKAMOTO, Satoshi AWATSUJI, Yasunori KONISHI, Tomonori WATANABE, Kazuhiro HARA, Junko KATSURAKU
  • Patent number: 12229914
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing highlight recovery. One of the methods includes receiving raw image data of an image, the raw image data comprising, for each of a plurality of highlight regions in the image, original channel values for one or more channels of the highlight region; processing the raw image data to generate updated image data, wherein the updated image data comprises updated channel values for each highlight region in the image, and wherein, for each of one or more highlight regions of the image, one or more updated channel values of the highlight region exceed a maximum channel value according to a predetermined data precision; and performing a hue correction process on the updated channel values of the one or more highlight regions of the image to generate final channel values that satisfy the predetermined data precision.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: February 18, 2025
    Assignee: Google LLC
    Inventor: Jun Nishimura
  • Patent number: 12125856
    Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: October 22, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Yoshihito Hara, Tohru Daitoh, Jun Nishimura, Kengo Hara, Yohei Takeuchi
  • Patent number: 12117706
    Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: October 15, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Kengo Hara, Tohru Daitoh, Yoshihito Hara, Jun Nishimura, Yohei Takeuchi
  • Publication number: 20240288738
    Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.
    Type: Application
    Filed: January 8, 2024
    Publication date: August 29, 2024
    Inventors: Kengo HARA, Tohru DAITOH, Yoshihito HARA, Jun NISHIMURA, Yohei TAKEUCHI
  • Patent number: 12057085
    Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: August 6, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Jun Nishimura, Kengo Hara, Yohei Takeuchi, Yoshihito Hara, Tohru Daitoh
  • Publication number: 20240257774
    Abstract: In each of unit circuits that constitute a shift register, a first conduction terminal of a second thin-film transistor that controls the output of an output signal serving as a scanning signal is given a second input clock signal having a amplitude larger than the amplitude of a first input clock signal that is given to a first conduction terminal of a first thin-film transistor that controls the output of an output signal serving as a control signal for controlling another unit circuit. The channel length of the second thin-film transistor is set to be greater than the channel length of the first thin-film transistor, so that the breakdown voltage of the second thin-film transistor is higher than the breakdown voltage of the first thin-film transistor.
    Type: Application
    Filed: December 5, 2023
    Publication date: August 1, 2024
    Inventors: Jun NISHIMURA, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Hideki Kitagawa, Masamitsu Yamanaka, Tohru Daitoh
  • Patent number: 12033599
    Abstract: Provided is an image display system that allows many persons to use multiple monitors without feeling color differences between the monitors. An image display system for displaying images on display devices includes multiple display devices, a spectral data acquisition unit, a candidate color matching function acquisition unit, a color difference calculation unit, and a color matching function selection unit. The spectral data acquisition unit is configured to acquire spectral data of the display devices. The candidate color matching function acquisition unit is configured to acquire multiple selection candidate color matching functions that are candidate color matching functions that may be selected by the color matching function selection unit. The color difference calculation unit is configured to calculate color differences between the display devices with respect to each of the selection candidate color matching functions using the spectral data.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 9, 2024
    Assignee: EIZO Corporation
    Inventors: Takao Maekawa, Kensuke Nagashima, Atsuyoshi Deyama, Yuito Mori, Jun Nishimura
  • Patent number: 12002820
    Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: June 4, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jun Nishimura, Akira Tagawa, Yohei Takeuchi, Yasuaki Iwase
  • Publication number: 20240169955
    Abstract: Provided is an image display system that allows many persons to use multiple monitors without feeling color differences between the monitors. An image display system for displaying images on display devices includes multiple display devices, a spectral data acquisition unit, a candidate color matching function acquisition unit, a color difference calculation unit, and a color matching function selection unit. The spectral data acquisition unit is configured to acquire spectral data of the display devices. The candidate color matching function acquisition unit is configured to acquire multiple selection candidate color matching functions that are candidate color matching functions that may be selected by the color matching function selection unit. The color difference calculation unit is configured to calculate color differences between the display devices with respect to each of the selection candidate color matching functions using the spectral data.
    Type: Application
    Filed: March 22, 2021
    Publication date: May 23, 2024
    Applicant: EIZO Corporation
    Inventors: Takao MAEKAWA, Kensuke NAGASHIMA, Atsuyoshi DEYAMA, Yuito MORI, Jun NISHIMURA
  • Patent number: 11955097
    Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 9, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Jun Nishimura, Yoshihito Hara, Yohei Takeuchi, Kengo Hara, Tohru Daitoh
  • Publication number: 20240112646
    Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 4, 2024
    Inventors: Jun NISHIMURA, Kengo HARA, Yohei TAKEUCHI, Yoshihito HARA, Tohru DAITOH
  • Patent number: 11830454
    Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: November 28, 2023
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Kengo Hara, Tohru Daitoh, Yoshihito Hara, Jun Nishimura, Yohei Takeuchi
  • Publication number: 20230352493
    Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 2, 2023
    Inventors: Yoshihito HARA, Tohru DAITOH, Jun NISHIMURA, Kengo HARA, Yohei TAKEUCHI
  • Publication number: 20230316463
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for using a filter for temporal noise reduction. In some implementations, image data for a series of frames, including a first input frame followed by a second input frame, of a video is obtained. A first output frame resulting from noise reduction processing for the first input frame and a measure of variance associated with a portion of the first output frame is obtained. An interpolation setting for noise reduction processing of a portion of the second input frame is determined. A second output frame is generated by interpolating the portion of the second input frame with the corresponding portion of the first output frame.
    Type: Application
    Filed: September 4, 2020
    Publication date: October 5, 2023
    Inventor: Jun Nishimura
  • Publication number: 20230252951
    Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.
    Type: Application
    Filed: January 25, 2023
    Publication date: August 10, 2023
    Inventors: Kengo HARA, Tohru DAITOH, Yoshihito HARA, Jun NISHIMURA, Yohei TAKEUCHI
  • Patent number: 11715437
    Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: August 1, 2023
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Yohei Takeuchi, Akira Tagawa, Yasuaki Iwase, Jun Nishimura
  • Publication number: 20230215395
    Abstract: A shift register includes stages each constituted by a unit circuit provided with thin-film transistors that separate a control node (i.e. a node that controls output from a unit circuit) into an output-side first control node and an input-side second control node. One of the thin-film transistors has a control terminal that is supplied with a set signal that is an output signal from a unit circuit constituting a preceding stage. The other of the thin-film transistors has a control terminal that is supplied with a reset signal that is an output signal from a unit circuit constituting a subsequent stage.
    Type: Application
    Filed: December 5, 2022
    Publication date: July 6, 2023
    Inventors: Jun NISHIMURA, Yoshihito HARA, Yohei TAKEUCHI, Kengo HARA, Tohru DAITOH
  • Publication number: 20230206875
    Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).
    Type: Application
    Filed: December 5, 2022
    Publication date: June 29, 2023
    Inventors: Jun NISHIMURA, Yoshihito HARA, Yohei TAKEUCHI, Kengo HARA, Tohru DAITOH