Abstract: An image forming apparatus is used in a post-payment system based on a customer's electronic money, and includes an image forming section, a communication section, and a controller. The image forming section performs a printing operation of forming an image on a sheet. The communication section performs communication so as to acquire settlement information including information that identifies the customer. The controller controls the image forming section and the communication section. As to the printing operation performed after acquisition of the settlement information, the controller settles a printing fee with a discount in a unit price per sheet in a situation where a printed sheet count is a predetermined number or more.

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation. [Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body disposed between the belt-like portions and stacked a plurality of first conductive layers via a first insulating layer, a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer, a first pillar extending in the first stacked body in a stacking direction of the first stacked body, and a plurality of second pillars extending in the stacking direction on both sides of the second stacked body facing the belt-like portions and arranged in the first direction, in which the second pillars each include a plate-like portion disposed at a height position of each of the first conductive layers, and the adjacent second pillars are connected to each other by the plate-like portion.

Abstract: A mechanism is described for facilitating hybrid tone mapping in camera systems according to one embodiment. A method of embodiments, as described herein, includes detecting a scene having a sequence of frames, and fusing the sequence of frames into a fused raw frame. The method may further include reconstructing the scene by performing global tone mapping and local tone mapping on the fused raw frame, and outputting an image reflecting the reconstructed scene based on the tone-mapped raw frame.

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

Abstract: In a server authentication process, a controller (a) transmits identification information of a consumable unit to an authentication server, and causes the authentication server to determine whether the consumable unit is a genuine product or not on the basis of the identification information and (b) receives the genuine product determination result from the authentication server. Further, (a) upon detecting replacement of the consumable unit, the controller reads identification information from a storage device of the consumable unit, performs the server authentication process based on the read identification information, and stores the received genuine product determination result into the non-volatile storage device, and (b) when powered on, the controller determines whether the consumable unit currently mounted is a genuine product or not on the basis of the genuine product determination result stored in the non-volatile storage device, without performing the server authentication process.

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: A semiconductor memory device comprises a substrate, first semiconductor films extending in a first direction crossing a surface of the substrate and arranged in a second direction and in a third direction, a conductive layer which covers peripheral faces of the first semiconductor films on a cross-section crossing the first direction, and a contact which extends in the first direction. Here, when straight lines disposed at equal intervals in the second direction on the cross-section and perpendicular to the second direction are defined as first to third straight lines, a first number of the first semiconductor films are provided on the first straight line, a second number less than the first number of the first semiconductor films are provided on the second straight line, a third number less than the second number of the first semiconductor films are provided on the third straight line.

Abstract: A unit circuit that constitutes a shift register includes a gate output lowering transistor (T01) whose source terminal is supplied with a second gate low voltage (Vgl2) and a gate output reset transistor (T03) Whose source terminal is supplied with a first gate low voltage (Vgl1), as constituent elements associated with the lowering of gate output. At the time of lowering the gate output, the gate output lowering transistor (T01) is made to be in an on state, and thereafter the gate output reset transistor (T03) is made to be in the on state. In this case, the gate terminal of the gate output reset transistor (T03) is supplied with a scanning signal or a signal having a waveform equivalent to that of the scanning signal outputted from the unit circuit in a subsequent stage.

Abstract: In each unit circuit constituting a shift register, as thin film transistors configured to lower a gate output, a thin film transistor whose state is controlled by a first reset signal and a thin film transistor whose state is controlled by a second reset signal are provided. Then, during the period in which a thin film transistor functioning as a buffer transistor is maintained in an ON state, the first reset signal changes from a low level to a high level, and then the second reset signal changes from a low level to a high level at a timing at which a corresponding gate bus line is to be changed from a selected state to an unselected state.

Abstract: When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.

Abstract: A semiconductor memory device according to an embodiment includes first to third conductive layers, first and second pillars, first and second contacts, and first to third members. The first pillar penetrates the first and second conductive layers in a first area. A second pillar penetrates the first and third conductive layers in the first area. The first and second contacts are provided on the second and third conductive layers respectively in a second area. The first and second members are provided between the second and third conductive layers in the first and second area, respectively. The third member penetrates the first conductive layers. The third member is in contact with each of the second and third conductive layers, and the first and second members.

Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.

Abstract: A mechanism is described for facilitating automatic tuning of image signal processors using reference images in image processing environments, according to one embodiment. A method of embodiments, as described herein, includes one or more processors to: receive images associated with one or more scenes captured by one or more cameras; access tuning parameters associated with functionalities within an image signal processor (ISP) pipeline; generate reference images based on the tuning parameters, wherein a reference image is associated with an image for each functionality within the ISP pipeline; and automatically tune the ISP pipeline based on selection of one or more of the reference images for one or more of the images for one or more of the functionalities.

Abstract: In a server authentication process, a controller (a) transmits identification information of a consumable unit to an authentication server, and causes the authentication server to determine whether the consumable unit is a genuine product or not on the basis of the identification information and (b) receives the genuine product determination result from the authentication server. Further, (a) upon detecting replacement of the consumable unit, the controller reads identification information from a storage device of the consumable unit, performs the server authentication process based on the read identification information, and stores the received genuine product determination result into the non-volatile storage device, and (b) when powered on, the controller determines whether the consumable unit currently mounted is a genuine product or not on the basis of the genuine product determination result stored in the non-volatile storage device, without performing the server authentication process.

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

Abstract: A liquid crystal display device of the present invention includes: a pair of substrates; a liquid crystal layer; a plurality of TFTs; a plurality of pixel electrodes; a common electrode placed in such a manner as to overlap the pixel electrodes via an insulating film; a color filter placed between the TFTs and the pixel electrodes and placed in such a manner as to overlap each of the plurality of pixel electrodes, that includes a plurality of colored portions that exhibit different colors from one another; and a light-blocking conducting film provided on an array substrate, placed closer to the liquid crystal layer than the TFTs while having a light blocking effect, placed in such a manner as to overlap a boundary portion between two adjacent colored portions of the plurality of colored portions, and electrically connected to the common electrode.

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film.

Abstract: When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn?1) scanned prior to the n-th scanning signal line.