Abstract: A scalable rank filter and method for performing rank filtering are disclosed. In one embodiment, the rank filter comprises a W staged pipeline with W stages to receive N input data samples and operable to generate an output based on the N input data samples as a result of the W stages completing execution, where W is a bit length of the inputs and W and N are integers greater than two; and output logic coupled to the W staged pipeline to determine the output prior to all W stages completing execution and to output the median.

Abstract: An image forming apparatus includes: a main body storage portion that stores control information which defines a control condition of an option device; and a main body control portion that makes a printing portion perform operation in accordance with the control condition of the option device, and based on the control condition of the option device, gives an operation instruction to an option control portion, wherein in a case where an unsuitableness error, the option control portion transmits the control information stored in the option storage portion to the main body control portion, and the main body control portion updates the control information such that the control information stored in the main body storage portion becomes the control information suitable for specifications of the option device.

Abstract: A person extraction unit extracts a person from an image input into an image input unit. An attribute extraction unit obtains an attribute of the person extracted by the person extraction unit. A motion path creation unit creates a motion path of the person from positional information within the image of the person extracted by the person extraction unit. A measurement reference coordinate setting unit sets a measurement line (a first measurement line to a third measurement line) for the motion path corresponding to the person according to the attribute of the person extracted by the attribute extraction unit. A people number counting unit counts the number of people based on positional relation between the motion path of the person created by the motion path creation unit and the measurement line set within the image.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.

Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.

Abstract: According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

Abstract: To provide a human attribute estimation system capable of improving estimation accuracy irrespective of an environment-dependent attribute is provided. An age/gender estimation system as a human attribute estimation system is provided with: a monitoring camera photographing a human targeted by attribute estimation and generating an image; an age/gender estimating section estimating an attribute of the human shown in the image generated by the monitoring camera using an estimation parameter; and an environment-dependent attribute specifying section specifying an environment-dependent attribute, which is an attribute dependent on an installation environment of the monitoring camera.

Abstract: An image forming apparatus includes: a main body storage portion that stores control information which defines a control condition of an option device; and a main body control portion that makes a printing portion perform operation in accordance with the control condition of the option device, and based on the control condition of the option device, gives an operation instruction to an option control portion, wherein in a case where an unsuitableness error, the option control portion transmits the control information stored in the option storage portion to the main body control portion, and the main body control portion updates the control information such that the control information stored in the main body storage portion becomes the control information suitable for specifications of the option device.

Abstract: According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

Abstract: A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.

Abstract: A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

Abstract: The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.

Abstract: A semiconductor device (100A) according to the present invention includes: a thin-film transistor (10); a first insulating layer (9) which has been formed over the thin-film transistor (10); a second insulating layer (11) which has been formed on the first insulating layer (9) and which has a hole (21a); and an opaque layer (12a) which is arranged so as to overlap an oxide semiconductor layer (5) when viewed along a normal to the substrate (1). The opaque layer (12a) has been formed in the hole (21a). The opaque layer (12a) has a raised and curved upper surface and the upper surface of the second insulating layer (11) is located closer to the substrate (1) than the upper surface of the opaque layer (12a) is.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.

Abstract: Provided is an image search system with which, while preserving search precision, it is possible to alleviate transmission volume. A search server acquires from a recorder only low-dimension data which normally has a low data volume. When the density of low-dimension image data within a feature space is greater than or equal to a prescribed threshold value, that is to say, when the number of dimensions for carrying out an inter-image identification with only the low-dimension data is insufficient, the search server acquires from the recorder high-dimension image data for the low-dimension data. Thus, while preserving search precision, it is possible to alleviate data transmission volume of a communication path.

Abstract: There is provided a person attribute estimation system capable of accurately estimating an attribute of a person according to an environment in which a person who is the target of attribute estimation is to be captured. The person attribute estimation system includes a camera, an attribute estimation unit for estimating an attribute of a person shown in the image generated by the camera, by using an estimation model, a pseudo-site image generation unit for generating a pseudo-site image by processing data of a standard image which is a person image according to image capturing environment data indicating an image capturing environment of the attribute estimation target person by the camera, and an estimation model relearning unit for performing learning of the estimation model by using the pseudo-site image.

Abstract: A post-processing device supplies a recoding medium when a punching unit is determined to have failed. The post-processing device allows the recording medium to be supplied to a stapling unit if passage of the recording medium supplied to the punching unit through an arrangement position of a second sensor is detected within a first time period after detection of passage of the recoding medium through an arrangement position of a first sensor.

Abstract: In some embodiments, a computer implemented method, a system, and/or a non-transitory computer readable medium can receive an actionable rule that represents user intent to share media data. The actionable rule can be analyzed to determine a set of conditions and a set of actions included in the actionable rule. The actionable rule, including the set of conditions and the set of actions, can be stored in a rule database. Context data can be acquired from a context database. Whether or not the set of conditions is satisfied based on the acquired context data can be determined. The set of actions can be executed when the set of conditions is satisfied based on the acquired context data. In some cases, executing the set of actions can include, at least in part, initiating a sharing of the media data with at least one target system.

Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array including memory cells, each of the memory cells disposed at each of intersections of first lines and second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell is applied with a first potential difference required in an operation of the selected memory cell. The control circuit is configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation, the number of selected memory cells simultaneously applied with the first potential difference can be changed.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.