Patents by Inventor Jun Shibata

Jun Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090270436
    Abstract: The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-b]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3: R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a n
    Type: Application
    Filed: January 8, 2008
    Publication date: October 29, 2009
    Inventors: Tomoharu Iino, Hideki Jona, Hideki Kurihara, Masayuki Nakamura, Kenji Niiyama, Jun Shibata, Tadashi Shimamura, Hitomi Watanabe, Takeru Yamakawa, Lihu Yang
  • Patent number: 7582950
    Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: September 1, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuhito Matsukawa, Tsuyoshi Koga, Akio Nishida, Yoshiko Higashide, Jun Shibata, Hiroshi Tobimatsu
  • Publication number: 20090137597
    Abstract: A quinoxalinone derivative of the formula (I): or a pharmaceutically acceptable salt or ester thereof, wherein; X is NH, S or the like; Y is O or the like; the partial structure is, for example, the formula: B1, B2, . . . , Bn?1 and Bn, (in which n is 4, 5 or 6) are each independently CH, N or the like; B?1, B?2, . . . , B?n?1 and B?n (in which n is 4, 5 or 6) are each independently hydrogen or the like; and R is hydrogen, lower alkyl or the like.
    Type: Application
    Filed: April 21, 2008
    Publication date: May 28, 2009
    Inventors: Hiroshi Hirai, Nobuhiko Kawanishi, Masaaki Hirose, Tetsuya Sugimoto, Kaori Kamijyo, Jun Shibata, Kouta Masutani
  • Publication number: 20090131464
    Abstract: The invention relates to a compound of a formula (I): or a pharmaceutically acceptable salt or ester thereof, useful as a therapeutic agent for various ACC-related disorders.
    Type: Application
    Filed: July 14, 2006
    Publication date: May 21, 2009
    Inventors: Takeru Yamakawa, Hideki Jona, Kenji Niiyama, Koji Yamada, Tomoharu Iino, Mitsuru Ohkubo, Hideaki Imamura, Jun Shibata, Jun Kusunoki, Lihu Yang
  • Patent number: 7410976
    Abstract: The invention relates to a compound of a formula (I): or a pharmaceutically acceptable salt or ester thereof, useful as a therapeutic agent for various ACC-related disorders.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: August 12, 2008
    Assignee: Merck & Co., Inc.
    Inventors: Takeru Yamakawa, Hideki Jona, Kenji Niiyama, Koji Yamada, Tomoharu Iino, Mitsuru Ohkubo, Hideaki Imamura, Jun Shibata, Jun Kusunoki, Lihu Yang
  • Publication number: 20080171761
    Abstract: The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of indole, 1H-indazole, 2H-indazole, 1H-thieno[2,3-c]pyrazole, 1H-pyrazolo[3,4-b]pyridine, benzo[b]furan, benzimidazole, benzoxazole, 1,2-benzisoxazole and imidazo[1,2-a]pyridine; R1 and R2 each represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a halo-C1-C6 alkoxy group, a cyclo-C3-C6 alkyloxy group, a C2-C7 alkanoyl group, a halo-C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, a halo-C2-C7 alkoxycarbonyl group, a cyclo-C3-C6 alkyloxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; an optionally-substituted C1-C6 alkyl, aryl or heterocyclic group; or a C1-C6 alkyl or C2-C6 alkenyl group having the aryl or heterocyclic group; R3 and R4 each represent a hydrogen atom, a halogen atom, a nitro group, a cyclo-C3-C
    Type: Application
    Filed: January 8, 2008
    Publication date: July 17, 2008
    Inventors: Tomoharu Iino, Hideki Jona, Jun Shibata, Tadashi Shimamura, Takeru Yamakawa, Lihu Yang
  • Patent number: 7388010
    Abstract: A quinoxalinone derivative of the formula (I): or a pharmaceutically acceptable salt or ester thereof, wherein; X is NH, S or the like; Y is O or the like; the partial structure is, for example, the formula: B1, B2, . . . , Bn?1 and Bn, (in which n is 4, 5 or 6) are each independently CH, N or the like; B?1, B?2, . . . , B?n?1 and B?n (in which n is 4, 5 or 6) are each independently hydrogen or the like; and R is hydrogen, lower alkyl or the like.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: June 17, 2008
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Hiroshi Hirai, Nobuhiko Kawanishi, Masaaki Hirose, Tetsuya Sugimoto, Kaori Kamijyo, Jun Shibata, Kouta Masutani
  • Publication number: 20080081811
    Abstract: The present invention relates to a compound represented by Formula [I]: wherein X is O, S, NH or CH2; Y1, Y2, Y3, Y4 and Y5, which may be identical or different, are each CH or N; however, at least one of Y1, Y2, Y3, Y4 and Y5 is N; Z1 and Z2, which may be identical or different, are each CH or N; n is an integer from 1 to 3; R1 is a C3-C8 cycloalkyl group, a C6-C10 aryl group, an aliphatic heterocyclic ring or an aromatic heterocyclic ring, or a bicyclic aliphatic saturated hydrocarbon group; R2 and R3, which may be identical or different, are each a hydrogen atom, a lower alkyl group, a lower alkenyl group, a C3-C8 cycloalkyl group, a C6-C10 aryl group, an aromatic heterocyclic ring, or the like; and R4 is a hydrogen atom, a lower alkyl group, a C3-C6 cycloalkyl group or the like, or a pharmaceutically acceptable salt or ester thereof, and a selective inhibitor against Cdk4 and/or Cdk6 or an anticancer agent containing the compound or a pharmaceutically acceptable salt or ester thereof.
    Type: Application
    Filed: May 19, 2005
    Publication date: April 3, 2008
    Applicant: BANYU PHARMACEUTICAL CO., LTD
    Inventors: Yoshikazu Iwasawa, Jun Shibata, Tadashi Shimamura, Hideki Kurihara, Takashi Mita, Nobuhiko Kawanishi, Takashi Hashihayata, Mikako Kawamura, Takeshi Sagara, Sachie Arai, Hiroshi Hirai
  • Publication number: 20070021453
    Abstract: The invention relates to a compound of a formula (I): or a pharmaceutically acceptable salt or ester thereof, useful as a therapeutic agent for various ACC-related disorders.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 25, 2007
    Inventors: Takeru Yamakawa, Hideki Jona, Kenji Niiyama, Koji Yamada, Tomoharu Iino, Mitsuru Ohkubo, Hideaki Imamura, Jun Shibata, Jun Kusunoki, Lihu Yang
  • Patent number: 7046960
    Abstract: While a spectrum waveform of an output signal from a subtracter (207) is visibly monitored, an operator controls a variable phases shifter (208) based upon a second control signal (CL2) so that a shape of a spectrum waveform of an output signal from a subtracter (207) is approximated to a spectrum waveform of a desirable wave to change a phase of a local oscillation frequency signal from a local oscillator (206). As a result, a phase of a duplicated loop signal is changed. Also, the operator controls a variable attenuator (209) based upon a first control signal (CL1) so that a shape of this spectrum waveform is approximated to a spectrum waveform of a desirable wave (20) to change a signal level of the duplicated loop signal.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 16, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Takemoto, Katsuyuki Kawase, Tetsu Takase, Jun Shibata
  • Publication number: 20060022321
    Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Kazuhito Matsukawa, Tsuyoshi Koga, Akio Nishida, Yoshiko Higashide, Jun Shibata, Hiroshi Tobimatsu
  • Publication number: 20060019959
    Abstract: A quinoxalinone derivative of the formula (I): or a pharmaceutically acceptable salt or ester thereof, wherein; X is NH, S or the like; Y is O or the like; the partial structure is, for example, the formula: B1, B2, . . . , Bn-1 and Bn, (in which n is 4, 5 or 6) are each independently CH, N or the like; B?1, B?2, . . . , B?n-1 and B?n (in which n is 4, 5 or 6) are each independently hydrogen or the like; and R is hydrogen, lower alkyl or the like.
    Type: Application
    Filed: October 27, 2003
    Publication date: January 26, 2006
    Applicant: Banyu Pharmaceutical Co., Ltd. Tsukuba Research Institute
    Inventors: Hiroshi Hirai, Nobuhiko Kawanishi, Masaaki Hirose, Tetsuya Sugimoto, Kaori Kamijyo, Jun Shibata, Kouta Masutani
  • Patent number: 6864587
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first pad, a second pad and a conductor. The first pad is formed on the interlayer insulating film and its circumferential edges are covered with a first surface-protecting film. The second pad formed on the interlayer insulating film facing the first pad across a second surface-protecting film, and its circumferential edges are covered with a third surface-protecting film. The conductor is provided continuously on the first pad, the first to third surface-protecting films, and the second pad.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Jun Shibata
  • Patent number: 6836007
    Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: December 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kazunari Michii, Jun Shibata
  • Publication number: 20040159925
    Abstract: In a semiconductor device, a first semiconductor including a substrate, and a semiconductor chip disposed on the major surface of the substrate and sealed with a resin; a wiring board; spacers disposed between the wiring board and the substrate; and a second semiconductor. At this time, the second semiconductor is electrically connected to the wiring board and disposed in the space formed by the wiring board, the substrate, and the spacer. The spacer is disposed so as to the first semiconductor to the wiring board electrically.
    Type: Application
    Filed: July 29, 2003
    Publication date: August 19, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tetsuya Matsuura, Kazunari Michii, Jun Shibata, Koji Bando
  • Patent number: 6770980
    Abstract: First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode is electrically connected only to the second electrode disposed on the back at position corresponding to the (N−1)-th chip select electrode, and the plurality of chip select electrodes are sporadically disposed in the first electrodes.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Jun Shibata
  • Publication number: 20040065944
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first pad, a second pad and a conductor. The first pad is formed on the interlayer insulating film and its circumferential edges are covered with a first surface-protecting film. The second pad formed on the interlayer insulating film facing the first pad across a second surface-protecting film, and its circumferential edges are covered with a third surface-protecting film. The conductor is provided continuously on the first pad, the first to third surface-protecting films, and the second pad.
    Type: Application
    Filed: March 18, 2003
    Publication date: April 8, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Jun Shibata
  • Publication number: 20040061211
    Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.
    Type: Application
    Filed: March 10, 2003
    Publication date: April 1, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kazunari Michii, Jun Shibata
  • Patent number: 6545365
    Abstract: A resin-sealed chip stack type semiconductor device comprises a substrate placed on many balls, a bottom chip to which wires are connected, a top chip to which wires are connected and mounted above the bottom chip, a non-conductive bonding layer which functions to bond and fix the two chips to each other, and a sealing resin which covers and protects all the components mounted on the substrate. The non-conductive bonding layer is provided by die bonding in such a manner that is at least covers the portion of the bottom chip where the corresponding wires are connected and does not allow generation of a gap between the two chips.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: April 8, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kondo, Koji Bando, Jun Shibata, Kazuko Narutaki
  • Publication number: 20030052399
    Abstract: First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode is electrically connected only to the second electrode disposed on the back at position corresponding to the (N−1)-th chip select electrode, and the plurality of chip select electrodes are sporadically disposed in the first electrodes.
    Type: Application
    Filed: August 19, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Jun Shibata