Patents by Inventor Jun Shibata

Jun Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5407228
    Abstract: A control system for an occupant restraint system including an airbag which is mounted on an automotive vehicle to protect a vehicle occupant from coming into direct contact with a steering wheel and/or a windshield. The control system comprises a control circuit including a microcomputer. The microcomputer is adapted to execute the following control. A decision is made to operate (inflate) the airbag when a vehicle deceleration exceeds a predetermined threshold level. The threshold level is changed at a timing which is set in accordance with a physical amount representative of a deceleration condition of the vehicle, thereby securely operating the airbag merely by making a simple adjustment to the control system.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: April 18, 1995
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Jun Shibata, Hiroaki Obayashi, Makoto Kimura, Shuzo Fukuzumi, Hironori Yoshikawa, Atsushi Hitotsumatsu, Yukio Hashimoto, Toshimi Yamanoi, Seiji Takaya
  • Patent number: 5315105
    Abstract: An optical operational memory device comprises a light-emitting device, a first and second phototransistors, and a load resistor. The light-emitting device and the first phototransistor are connected electrically in series to form an optical bistable switch based on optical positive feedback. The second phototransistor is connected in parallel to the optical bistable switch, and the load resistor is connected in series to the optical bistable switch. The time constant given by the product of the current gain of the second phototransistor, the base-collector capacitance of the second phototransistor, and the resistance of the load resistor is larger than the period required for recombination of the excess majority carriers in the base of the first phototransistor. A single optical beam modulated with pulse signals is input to the first and the second phototransistors simultaneously.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: May 24, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Matsuda, Jun Shibata
  • Patent number: 5308440
    Abstract: A semiconductor device with air-bridge interconnection comprises: a substrate; a plurality of mesas with distance therebetween smaller than a predetermined value; and a metal layer supported by the plurality of mesas, the metal layer having a narrow portion at the intermediate portion thereof and both ends having larger width than the narrow portion. The air-bridge interconnection is obtained by side-etching controlled during dry-etching using interconnection metal layer as an etching-mask to remove a mass of semiconductor material under the interconnection metal layer.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: May 3, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoji Chino, Kenichi Matsuda, Jun Shibata
  • Patent number: 5309021
    Abstract: A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: May 3, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Haruo Shimamoto, Jun Shibata, Toru Tachikawa, Tetsuya Ueda, Hiroshi Seki
  • Patent number: 5233556
    Abstract: An optoelectronic memory and logic device has a function of a reset-set flip-flop (RS-FF) or an exclusive-OR (EOR) gate. The RS-FF includes a first and a second optical inverter circuits. The optical inverter circuit includes a parallel connection of a light emitting device and a phototransistor, and a load resistor connected in series. The phototransistor in the first (second) optical inverter circuit receives the light from the lihgt emitting device in the second (first) optical inverter circuit. The RS-FF has high contrast ratio in case of emitting high output power, and operates stably when the load resistance and the bias voltage are fluctuated. The EOR gate comprises a parallel connection of an adder circuit and a multiplier circuit, and a load resistor connected in series. The adder circuit is a series connection of a light emitting device and a first phototransistor. The multiplier circuit is a series connection of a second phototransistor and a third phototransistor.
    Type: Grant
    Filed: January 28, 1992
    Date of Patent: August 3, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Matsuda, Jun Shibata
  • Patent number: 5222449
    Abstract: A sewing machine comprises a feeding device which moves between the under position of the cutter apparatus and the under position of the needle bar with a work piece which is set on the feeding device such that the buttonhole slit is formed on a desired position, a setting signal transmitter for transmitting a complete signal when the work piece is set on the feeding device, and a post-buttonhole slit method indicator for indicating the post-buttonhole slit method in order to form the buttonhole slit by the cutter apparatus after buttonhole stitches are formed by the cooperation of the needle and the looper. When the post-buttonhole slit method is indicated by the post-buttonhole slit method indicator, the feeding device moves under the needle bar and the feeding device is controlled so as to stay under the needle bar until the setting signal transmitter inputs the complete signal.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: June 29, 1993
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Kazuaki Koie, Hideo Ando, Akihiro Funahashi, Jun Shibata
  • Patent number: 5170219
    Abstract: An optical heterodyne interference type detecting apparatus for measuring a displacement characteristic of a workpiece, including a device for applying a controlled physical quantity to the workpiece to induce a displacement of the workpiece, an optical heterodyne interference type displacement detecting device for detecting a difference in one of a frequency and a phase between a measuring light beam reflected by the portion of the workpiece and a reference light beam, and thereby detecting an amount of the displacement of the workpiece, and an arithmetic and control device for obtaining the displacement characteristic of the workpiece, based on the physical quantity and the amount of displacement detected by the displacement detecting device.
    Type: Grant
    Filed: January 30, 1991
    Date of Patent: December 8, 1992
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Jun Shibata
  • Patent number: 5109785
    Abstract: A feeding device for independently feeding, by a preparatory device, a binder strip and flap strips to a garment held by a base presses. There are eight types of combination in feeding fashions, whether or not the binder strip is to be fed, whether or not one flap strip is to be fed, and whether or not another flap strip is to be fed (2.sup.3 =8). Various feeding fashions are provisionally set in order prior to actual sewing, and control means controls actual operations of the preparatory device in accordance with the feeding fashions and every feeding fashions.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: May 5, 1992
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Kazushi Inoue, Shigeru Abe, Yuji Tagawa, Takashi Kondo, Yasuhiko Watanabe, Jun Shibata
  • Patent number: 5095200
    Abstract: An optoelectronic memory, logic, and interconnection device having an optical bistable circuit as an essential element. The optical bistable circuit includes an optical bistable switch which is a light emitting device and a first phototransistor detecting the light emitted from the light emitting device, connected in series, a second phototransistor connected in parallel to the optical bistable switch which does not detect the light emitted from the light emitting device, and a load resistor connected in series to the optical bistable switch. The optoelectronic memory, logic, and interconnection device operates as an optoelectronic memory device turned on and off with the same light source, as an optoelectronic logic device executing exclusive OR operation, or as a light source for reconfigurable optical interconnection.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: March 10, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Matsuda, Jun Shibata
  • Patent number: 5014096
    Abstract: An optoelectronic integrated circuit including an optical bistable circuit comprises: an optical gate device responsive to a current injected to an active layer thereof and to a first ray transmitted through the active layer for emitting first and second light rays and for controlling intensity of the first light ray in accordance with the current; and a first phototransistor serially connected with the optical gate device so arranged to receive the second light ray for causing the current to flow through the optical gate device in response to the second light ray and a set signal light ray, the first phototransistor holding flowing of the current when the second light ray is emitted. This circuit can control the first light ray incident to the optical gate device in response to a set signal light ray applied to the first phototransistor. A second phototransistor may be included for stopping emission of light by the optical gate device in response to a reset signal light ray.
    Type: Grant
    Filed: February 1, 1990
    Date of Patent: May 7, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Matsuda, Jun Shibata
  • Patent number: 4956682
    Abstract: An optoelectronic integrated circuit includes an N.sup.+ type cladding layer, an N type cladding layer, an active layer smaller in band gap than the N type cladding layer and a P type waveguide greater in band gap than the active layer sequentially formed on a semi-insulating substrate, a P type cladding layer partially formed on the surface of the P type waveguide, a laser composed of these N.sup.+ type and N type cladding layers, active layer, waveguide and P type cladding layer, and an N type emitted layer wider in band gap than the P type waveguide formed partially on the surface of the P type waveguide, thereby composing a heterojunction bipolar transistor using the N type cladding layer as the collector and the P type waveguide as the base.
    Type: Grant
    Filed: February 10, 1988
    Date of Patent: September 11, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Ohnaka, Hiraaki Tsujii, Yoichi Sasai, Jun Shibata
  • Patent number: 4922497
    Abstract: An optical logic circuit which is high in operation speed, low in power dissipation, and capable of operating at room temperature, possesses a semiconductor laser biased at a constant current higher than a threshold current. A light input is injected into the laser, the light input differing in the polarization direction of its oscillation mode. The output light of the semiconductor laser has a bistability characteristic with respect to the light input.
    Type: Grant
    Filed: February 7, 1989
    Date of Patent: May 1, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Mori, Jun Shibata
  • Patent number: 4779283
    Abstract: A semiconductor laser in which an InGaAsP active layer serving as light emitting layer and formed in the shape of a stripe on the surface of a flat InP first clad layer, and an InP second clad layer that is wider than the InGaAsP active layer and formed on the InGaAsP active layer are buried in an InP burying layer. The stripe direction is the <011> direction, an etched mirror is formed in the vicinity of the end of the active layer, and an opto-electronic integrated circuit is formed by integrating the electric device and photo detecting device on the same substrate. The substrate is a semi-insulating substrate, and the electric device and photo detecting device are formed on the InGaAsp or InGaAs layer formed on the InP burying layer by crystal growth.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: October 18, 1988
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Ohnaka, Jun Shibata, Yoichi Sasai, Ichiro Nakao
  • Patent number: 4710936
    Abstract: A semiconductor laser device has a double hetero construction such that a direct transition type semiconductor layer having a high refractive index is placed between direct transition type semiconductor layers having a low refractive index, and has an optical resonator formed in the direct transition type semiconductor layer of a high refractive index for enabling lasing operation. The condition of lasing is controllable by the transistor of the double hetero construction. The semiconductor laser device is of transistor structure and yet it constitutes integrated circuits for lasing. As an optoelectronic device, it can be advantageously employed in optical-fiber communication systems and optical information systems.
    Type: Grant
    Filed: April 12, 1985
    Date of Patent: December 1, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Shibata, Hiroyuki Serizawa
  • Patent number: 4441198
    Abstract: A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: April 3, 1984
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Shibata, Haruyasu Yamada, Toshiki Mori, Toyoki Takemoto