Patents by Inventor Jun Shibata

Jun Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020127968
    Abstract: While a spectrum waveform of an output signal from a subtracter (207) is visibly monitored, an operator controls a variable phases shifter (208) based upon a second control signal (CL2) so that a shape of a spectrum waveform of an output signal from a subtracter (207) is approximated to a spectrum waveform of a desirable wave to change a phase of a local oscillation frequency signal from a local oscillator (206). As a result, a phase of a duplicated loop signal is changed. Also, the operator controls a variable attenuator (209) based upon a first control signal (CL1) so that a shape of this spectrum waveform is approximated to a spectrum waveform of a desirable wave (20) to change a signal level of the duplicated loop signal.
    Type: Application
    Filed: October 24, 2001
    Publication date: September 12, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Takemoto, Katsuyuki Kawase, Tetsu Takase, Jun Shibata
  • Patent number: 6445064
    Abstract: A semiconductor device includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands on an upper surface for mounting the second semiconductor package and lands on the lower surface for external connection, which are used for connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 3, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Ishii, Kazunari Michii, Jun Shibata, Moriyoshi Nakashima
  • Publication number: 20020105091
    Abstract: A semiconductor device of the present invention includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands, on the upper surface, for mounting the second semiconductor package and lands, on the lower surface, for external connection, which are used for the connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.
    Type: Application
    Filed: July 18, 2001
    Publication date: August 8, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Ishii, Kazunari Michii, Jun Shibata, Moriyoshi Nakashima
  • Publication number: 20010035587
    Abstract: A resin-sealed chip stack type semiconductor device comprises a substrate placed on many balls, a bottom chip to which wires are connected, a top chip to which wires are connected and mounted above the bottom chip, a non-conductive bonding layer which functions to bond and fix the two chips to each other, and a sealing resin which covers and protects all the components mounted on the substrate. The non-conductive bonding layer is provided by die bonding in such a manner that is at least covers the portion of the bottom chip where the corresponding wires are connected and does not allow generation of a gap between the two chips.
    Type: Application
    Filed: February 13, 2001
    Publication date: November 1, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kondo, Koji Bando, Jun Shibata, Kazuko Narutaki
  • Patent number: 6256875
    Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: July 10, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
  • Patent number: 6071755
    Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate to a transferring substrate on which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: June 6, 2000
    Assignee: Mitsubushi Denki Kabushiki Kaisha
    Inventors: Shinji Baba, Jun Shibata, Tetsuya Ueda
  • Patent number: 6046071
    Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: April 4, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
  • Patent number: 6005289
    Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: December 21, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
  • Patent number: 5969426
    Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate on a transferring substrate to which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: October 19, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Baba, Jun Shibata, Tetsuya Ueda
  • Patent number: 5834340
    Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
  • Patent number: 5777150
    Abstract: A compound of the formula (I) or its pharmaceutically acceptable salt or ester: ##STR1## wherein each of ##STR2## which are the same or different, is an aryl group or a heteroaromatic ring group; A is a C.sub.3-8 linear saturated or unsaturated aliphatic hydrocarbon group which may have substituent(s) selected from the group consisting of a lower alkyl group, a hydroxyl group, a lower alkoxy group, a carboxyl group, an aryl group and an aralkyl group; Q is a single bond or a group of the formula --CO--O--, --O--CO--, --CH.sub.2 CH.sub.2 --, --CH.dbd.CH--, --OCH.sub.2 --, --SCH.sub.2 --, --CH.sub.2 O-- or --CH.sub.2 S--; each of R.sup.1, R.sup.2, R.sup.3 and R.sup.4 which are the same or different, is a hydrogen atom, a halogen atom, a lower alkyl group, a hydroxyl group, a lower alkoxy group, or an aryl or heteroaromatic ring group which may have substituent(s) selected from the group consisting of a halogen atom, a lower alkyl group and a lower alkoxy group; each of R.sup.5, R.sup.6 and R.sup.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: July 7, 1998
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Takashi Nomoto, Masahiro Hayashi, Jun Shibata, Yoshikazu Iwasawa, Morihiro Mitsuya, Yoshiaki Iida, Katsumasa Nonoshita, Yasufumi Nagata
  • Patent number: 5731631
    Abstract: A semiconductor device having improved heat dissipation property and electrical characteristics and applicable to an integrated circuit having a multiplicity of electrodes, and a method of fabricating the semiconductor device are disclosed. A surface of a semiconductor chip (1) on which a bump (2) is formed is in face to face relation to a surface of a circuit substrate (3) on which a land (5) is formed. A polyimide tape (6) and a TAB lead (7) constitute a TAB tape. The bump (2) and the land (5) are electrically connected to each other through the flat TAB tape. The land (5) is electrically connected to an external connection electrode (4) through an interconnecting line within the circuit substrate (3). The TAB lead (7) extending from the bump (2) to the land (5) is reduced in length, and the signal through the TAB lead (7) accordingly has improved electrical characteristics.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: March 24, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yomiyuki Yama, Masao Kobayashi, Jun Shibata, Shinji Baba, Masaki Watanabe
  • Patent number: 5710062
    Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: January 20, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
  • Patent number: 5701033
    Abstract: A semiconductor device comprising a substrate having a hollow cavity for mounting a semiconductor element therein and a lowered step surface at a periphery of the cavity for mounting a chip component thereon. A semiconductor element is mounted within the cavity and a chip capacitor is mounted to the lowered step surface. The semiconductor element and the chip component are adapted to be connected to an external circuit through electrical conductors. A cap is attached to the substrate and a seal material is filled into a space defined between the cap and the substrate for sealing the cavity and for encapsulating the chip component on the lowered step surface which may extend along the entire periphery of the cavity. The cap may include a projection adapted to abut gainst a side wall of the lowered step surface, or alternatively, the lowered step surface may include a side wall having a projection adapted to abut against periphery of the cap.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: December 23, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Jun Shibata, Yomiyuki Yama
  • Patent number: 5616803
    Abstract: A compound of the formula (I) or its pharmaceutically acceptable salt or ester: ##STR1## wherein each of the substituents are herein defined.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: April 1, 1997
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Takashi Nomoto, Masahiro Hayashi, Jun Shibata, Yoshikazu Iwasawa, Morihiro Mitsuya, Yoshiaki Iida, Katsumasa Nonoshita, Yasufumi Nagata
  • Patent number: 5606101
    Abstract: A compound of the formula (I) or its pharmaceutically acceptable salt or ester: ##STR1## and intermediates thereof.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: February 25, 1997
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Takashi Nomoto, Masahiro Hayashi, Jun Shibata, Yoshikazu Iwasawa, Morihiro Mitsuya, Yoshiaki IIda, Katsumasa Nonoshita, Yasufumi Nagata
  • Patent number: 5554887
    Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: September 10, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
  • Patent number: 5542700
    Abstract: A control system for an occupant restraint system mounted on the vehicle including an air-bag to protect the vehicle occupant from direct contact with a steering wheel or a windshield, comprises a control circuit for detecting deceleration of the vehicle, for integrating the value obtained by subtracting a predetermined integration offset from the deceleration to obtain an integrated value, for making a decision to operate the occupant restraint system when the integrated value exceeds a predetermined threshold level, for calculating a physical amount representative of a deceleration condition of the vehicle, for setting a changing timing at which the integration offset is changed in accordance with the physical amount, and for changing the integration offset of the changing timing.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: August 6, 1996
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Jun Shibata, Hiroaki Obayashi, Makoto Kimura, Shuzo Fukuzumi, Hironori Yoshikawa, Atsushi Hitotsumatsu, Yukio Hashimoto, Toshimi Yamanoi, Seiji Takaya
  • Patent number: 5493493
    Abstract: A control system for a passenger protecting apparatus includes: a sensor (100) for detecting vehicle deceleration values; a calculating section (101) for calculating a deceleration dispersion value (Bu) on the basis of the detected deceleration values; a deciding section (103) for deciding whether the passenger protecting apparatus is activated or not, on the basis of the calculated deceleration dispersion value; and a drive and control section (104) for activating the passenger protecting apparatus when the activating section decides the activation of the passenger protecting apparatus (102). The control system can activate an air bag module or seat belt reliably in any collision modes by a simple adjustment.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: February 20, 1996
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Jun Shibata, Hiroaki Oobayashi, Makoto Kimura, Syuuzo Fukuzumi
  • Patent number: 5488149
    Abstract: A compound of the formula (I) or its pharmaceutically acceptable salt or ester: ##STR1## wherein each of the substituents are herein defined.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 30, 1996
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Takashi Nomoto, Masahiro Hayashi, Jun Shibata, Yoshikazu Iwasawa, Morihiro Mitsuya, Yoshiaki Iida, Katsumasa Nonoshita, Yasufumi Nagata