Patents by Inventor Jun-Wei Chen

Jun-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200082780
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung CHIN, Ching-Yi HSU, Chang-He LIU, Chih-Cherng LIAO, Jun-Wei CHEN, Leuh FANG
  • Patent number: 10504758
    Abstract: A nozzle for emitting a fluid comprises a channel, a light source and a light sensor. The channel is configured to flow the fluid. The light source is configured to emit light towards a surface on which the fluid is applied and the light sensor is configured to receive reflected light from the surface.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kai-Lin Chuang, Tsung-Chi Chen, Pei-Jung Chang, Chun-Wei Huang, Jun Xiu Liu
  • Publication number: 20190019472
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 17, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung CHIN, Ching-Yi HSU, Chang-He LIU, Chih-Cherng LIAO, Jun-Wei CHEN, Leuh FANG
  • Patent number: 9985019
    Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 29, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9666699
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 30, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jun-Wei Chen
  • Publication number: 20170077091
    Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 16, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Jun-Wei CHEN
  • Patent number: 9553091
    Abstract: A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Ching-Yi Hsu, Jun-Wei Chen
  • Patent number: 9548354
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Po-Heng Lin, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9530900
    Abstract: A Schottky diode is provided, which includes a well of a first conductive type and a lightly doped region of a second conductive type on the well, wherein the first conductive type is opposite to the second conductive type. The Schottky diode includes a heavily doped region of the second conductive type on the well, and a gate structure on a part of the lightly doped region. The gate structure includes a gate electrode and a gate dielectric layer. The lightly doped region not covered by the gate structure and the heavily doped region are disposed at two opposite sides of the gate structure, respectively. The Schottky diode includes a first contact electrically connecting the heavily doped region and a first electrode, a second contact electrically connecting the gate electrode and a second electrode, and a third contact electrically connecting the lightly doped region and the second electrode.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: December 27, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9525045
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate having a first conductive type and an epitaxial layer having the first conductive type disposed over the substrate, wherein a trench is formed in the epitaxial layer. The semiconductor device also includes a polysilicon layer having the first conductive type disposed in the trench. The semiconductor device further includes a doped region having a second conductive type disposed along a sidewall and a bottom of the trench in the epitaxial layer, wherein a thickness along the sidewall and the bottom of the trench is uniform, and wherein the thickness is a vertical distance between the outermost side of the trench to the sidewall or the bottom of the trench.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 20, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chia-Hao Lee, Pei-Heng Hung, Chih-Cherng Liao, Jun-Wei Chen
  • Publication number: 20160017228
    Abstract: A liquid-crystal film includes a liquid crystal mixture with the gel state. The liquid crystal mixture is formed of at least one ?-conjugated polymer gelator and a liquid-crystal unit. The concentration of the at least one ?-conjugated polymer gelator is 0.05-5 wt %. The concentration of the liquid-crystal unit is 95-99.95 wt %. The at least one ?-conjugated polymer gelator is aligned through the liquid-crystal unit and combined together to form a plurality of fibers. The fibers include at least 60% arranged regularly in direction and some of the fibers are linked with one another to form a network structure.
    Type: Application
    Filed: December 24, 2014
    Publication date: January 21, 2016
    Inventors: Chih-Yu CHAO, Jun-Wei CHEN, Chiu-Chang HUANG
  • Patent number: 8659086
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 25, 2014
    Assignee: Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Patent number: 8338217
    Abstract: A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 25, 2012
    Assignee: Au Optronics Corporation
    Inventors: Yen-Cheng Hu, Cheng-Chang Kuo, Jun-Wei Chen, Hsin-Feng Li, Jen-Chieh Chen, Zhen-Cheng Wu
  • Publication number: 20120171805
    Abstract: A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 5, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Yen-Cheng Hu, Cheng-Chang Kuo, Jun-Wei Chen, Hsin-Feng Li, Jen-Chieh Chen, Zhen-Cheng Wu
  • Patent number: 8097522
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: January 17, 2012
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan, Jun-Wei Chen, HyungSik Ryu
  • Patent number: 7994578
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 9, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong)
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Patent number: 7956437
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: June 7, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
  • Patent number: 7812393
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 12, 2010
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
  • Patent number: 7738224
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 15, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Patent number: 7719054
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: May 18, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu