Patents by Inventor Jun-Wei Chen

Jun-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070043189
    Abstract: This invention relates to an amphoteric copolymer, and the use of the copolymer to improve the fluidity and fluidity retention of cementitious materials. The chemical structure of the copolymer is as follows: wherein R1 is H or CH3; R2 is a hydrogen atom, or an alkyl group, a cyclic aliphatic group or an aryl group, having 1 to 10 carbon atoms; D is H or COOR3, R3 is a hydrogen atom, or an alkyl group, a cyclic aliphatic group or an aryl group, having 1 to 10 carbon atoms, or a cationic salt group; Z is an O atom or an NH group; A is a —COO group, a —SO3 group or an acid form; a, b, or c is an integer from 1 to 5000; and p and q are integers from 1 to 10.
    Type: Application
    Filed: April 19, 2006
    Publication date: February 22, 2007
    Inventors: Kung-Chung Hsu, Fu-Ti Jiang, Jun-Wei Chen
  • Patent number: 5751054
    Abstract: A semiconductor structure which includes zener diodes and various combinations of MOS transistors, bipolar transistors and DMOS transistors, all fabricated on the same integrated circuit chip
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Siliconix incorporated
    Inventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun Wei Chen
  • Patent number: 5648281
    Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: July 15, 1997
    Assignee: Siliconix incorporated
    Inventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun Wei Chen
  • Patent number: 5643820
    Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: July 1, 1997
    Assignee: Siliconix incorporated
    Inventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun Wei Chen
  • Patent number: 5439842
    Abstract: A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: August 8, 1995
    Assignee: Siliconix Incorporated
    Inventors: Mike F. Chang, David G. Grasso, Jun-Wei Chen
  • Patent number: 5328866
    Abstract: A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: July 12, 1994
    Assignee: Siliconix Incorporated
    Inventors: Mike F. Chang, David G. Grasso, Jun-Wei Chen