Patents by Inventor Jun-Xiu Liu
Jun-Xiu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210232745Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.Type: ApplicationFiled: November 24, 2020Publication date: July 29, 2021Inventors: Chung-Pin CHOU, Chun-Wen WANG, Meng Ku CHI, Yan-Cheng CHEN, Jun-Xiu LIU
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Patent number: 11031266Abstract: A method includes disposing a wafer carrier onto a load port; detecting, by a first sensor in the wafer carrier, an elevation of a slot in the wafer carrier; adjusting an elevation of a wafer transferring device according to the detected elevation of the slot; and moving, at the adjusted elevation of the wafer transferring device, a wafer to the slot by the wafer transferring device.Type: GrantFiled: June 21, 2019Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Liao, Shiao-Ching Wu, Jun-Xiu Liu
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Patent number: 11017522Abstract: A system includes an inspection device and an image processing unit. The inspection device is configured to scan a wafer to generate an inspected image. The image processing unit is configured to receive the inspected image, and is configured to analyze the inspected image by using at least one deep learning algorithm in order to determine whether there is any defect image shown in a region of interest in the inspected image. When there is at least one defect image shown in the region of interest in the inspected image, the inspection device is further configured to magnify the region of interest in the inspected image to generate a magnified inspected image for identification of defects.Type: GrantFiled: April 18, 2019Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Pin Chou, In-Tsang Lin, Sheng-Wen Huang, Yu-Ting Wang, Jui-Kuo Lai, Hsin-Hui Chou, Jun-Xiu Liu, Tien-Wen Wang
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Publication number: 20210027984Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Chung-Pin CHOU, Sheng-Wen HUANG, Jun-Xiu LIU
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Publication number: 20200395220Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: ApplicationFiled: August 21, 2020Publication date: December 17, 2020Inventors: Han-Wen LIAO, Jun-Xiu LIU, Chun-Chih LIN
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Publication number: 20200388020Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A plurality of raw images of the semiconductor wafer are obtained according to GDS information regarding a layout of a target die, by an inspection apparatus. A first image-based comparison is performed on the raw images, so as to provide a comparison result, by a determining circuitry. The comparison result indicates whether an image difference is present between the images. One of the raw images having the image difference is assigned as a defect image. A second image-based comparison is performed on a reference image and the defect image, so as to classify a defect type of the image difference, by the determining circuitry. The layout of the target die includes a circuit with a duplicate layout formed by a plurality of same cells. The number of the plurality of raw images is greater than 2.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Yen-Liang CHEN, Jun-Xiu LIU
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Patent number: 10825650Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: GrantFiled: June 3, 2019Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Pin Chou, Sheng-Wen Huang, Jun-Xiu Liu
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Publication number: 20200334800Abstract: A system includes an inspection device and an image processing unit. The inspection device is configured to scan a wafer to generate an inspected image. The image processing unit is configured to receive the inspected image, and is configured to analyze the inspected image by using at least one deep learning algorithm in order to determine whether there is any defect image shown in a region of interest in the inspected image. When there is at least one defect image shown in the region of interest in the inspected image, the inspection device is further configured to magnify the region of interest in the inspected image to generate a magnified inspected image for identification of defects.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Pin CHOU, In-Tsang LIN, Sheng-Wen HUANG, Yu-Ting WANG, Jui-Kuo LAI, Hsin-Hui CHOU, Jun-Xiu LIU, Tien-Wen WANG
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Patent number: 10784114Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: GrantFiled: October 31, 2019Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Jun-Xiu Liu, Chun-Chih Lin
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Patent number: 10755405Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A first raw image, a second raw image, and a third raw image of the semiconductor wafer are obtained by an inspection apparatus according to graphic data system (GDS) information regarding layout of a target die. A first image-based comparison is performed by a determining circuitry on the first, second, and third raw images, so as to provide a comparison result. The comparison result indicates whether an image difference is present between the first, second, and third raw images.Type: GrantFiled: March 13, 2018Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Liang Chen, Jun-Xiu Liu
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Publication number: 20200130134Abstract: A polish head of a chemical mechanical polishing system is provided. The polish head includes a carrier head, a membrane mounted to the carrier head, an inner retaining ring mounted to the carrier head and surrounding the membrane, an outer retaining ring mounted to the carrier head and surrounding the inner retaining ring, and an image capturing device. The outer retaining ring is spaced apart from the inner retaining ring. The image capturing device is mounted to the carrier head and between the inner retaining ring and the outer retaining ring.Type: ApplicationFiled: October 18, 2019Publication date: April 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Liang CHEN, Jun-Xiu LIU, Chia-Hsien CHOU
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Publication number: 20200118852Abstract: A method of monitoring a fluid includes: applying the fluid from within a nozzle to a surface of a wafer outside of the nozzle; emitting light, by a light source, from the nozzle to the surface; receiving light reflected from the surface by a light sensor and causing the reflected light to propagate into the nozzle; and determining whether a variation of the fluid occurs according to the reflected light.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: KAI-LIN CHUANG, TSUNG-CHI CHEN, PEI-JUNG CHANG, CHUN-WEI HUANG, JUN XIU LIU
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Publication number: 20200066538Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Inventors: Han-Wen LIAO, Jun Xiu LIU, Chun-Chih LIN
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Publication number: 20200020558Abstract: A method includes disposing a wafer carrier onto a load port; detecting, by a first sensor in the wafer carrier, an elevation of a slot in the wafer carrier; adjusting an elevation of a wafer transferring device according to the detected elevation of the slot; and moving, at the adjusted elevation of the wafer transferring device, a wafer to the slot by the wafer transferring device.Type: ApplicationFiled: June 21, 2019Publication date: January 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung LIAO, Shiao-Ching WU, Jun-Xiu LIU
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Patent number: 10504758Abstract: A nozzle for emitting a fluid comprises a channel, a light source and a light sensor. The channel is configured to flow the fluid. The light source is configured to emit light towards a surface on which the fluid is applied and the light sensor is configured to receive reflected light from the surface.Type: GrantFiled: February 14, 2014Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kai-Lin Chuang, Tsung-Chi Chen, Pei-Jung Chang, Chun-Wei Huang, Jun Xiu Liu
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Patent number: 10504737Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: GrantFiled: August 25, 2017Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Jun Xiu Liu, Chun-Chih Lin
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Publication number: 20190252181Abstract: A method includes disposing a semiconductor substrate over a chuck. The chuck has a plurality of holes therein. The semiconductor substrate has a first surface facing the chuck and a second surface opposite thereto. A liquid layer is formed flowing over a top surface of the chuck by supplying liquid to the top surface of the chuck through the holes of the chuck. The semiconductor substrate is moved toward the chuck such that the first surface of the semiconductor substrate is in contact with the liquid layer and the liquid layer flows between the first surface of the semiconductor substrate and the top surface of the chuck.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chih HSU, Kai-Lin CHUANG, Yuan-Chi CHIEN, Jeng-Huei YANG, Jun-Xiu LIU
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Publication number: 20190164264Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A first raw image, a second raw image, and a third raw image of the semiconductor wafer are obtained by an inspection apparatus according to graphic data system (GDS) information regarding layout of a target die. A first image-based comparison is performed by a determining circuitry on the first, second, and third raw images, so as to provide a comparison result. The comparison result indicates whether an image difference is present between the first, second, and third raw images.Type: ApplicationFiled: March 13, 2018Publication date: May 30, 2019Inventors: Yen-Liang CHEN, Jun-Xiu LIU
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Patent number: 10269557Abstract: An apparatus of processing a semiconductor substrate include a chuck, a holder, a liquid supplying system and a positive pressure unit. The chuck has a principal surface and at least a hole formed thereon. The holder is capable of holding a semiconductor substrate at a position above the principal surface. The liquid supplying system is configured to provide a liquid film onto the principal surface through the hole. The positive pressure unit is configured for providing a gas flow to a space over the chuck. A method of processing a semiconductor substrate is disclosed herein as well.Type: GrantFiled: October 20, 2015Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chih Hsu, Kai-Lin Chuang, Yuan-Chi Chien, Jeng-Huei Yang, Jun-Xiu Liu
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Publication number: 20180350614Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: ApplicationFiled: August 25, 2017Publication date: December 6, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Wen Liao, Jun Xiu Liu, Chun-Chih Lin