Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Abstract: The invention provides gastric residence systems with specifically tailored architectures and methods for making such systems. The components of the gastric residence systems can be manufactured by three-dimensional printing or by co-extrusion. The ability to construct precise architectures for the systems provides excellent control over drug release, in vivo stability, and residence time of the systems.

Abstract: Provided are an artificial intelligence system for simulating functions and so forth of human brains by using a mechanical learning algorithm. A method, performed by a device, of providing a notification message about a call request may include one or more of receiving the call request from another device, obtaining context information about a situation of a user if a user input accepting the call request is not received within a preset time, determining a reason for a non-response of the user by analyzing the context information, obtaining information about a relationship between the user and another user of the other device, generating a notification message describing the reason for the non-response based on the context information, determining whether to transmit the notification message to the other device based on the reason for the non-response and the information about the relationship, and transmitting the notification message to the other device based on the determination.

Abstract: Disclosed are an organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes a thin-film transistor including source and drain electrodes, a first electrode formed by extending the source or drain electrode, a passivation layer and a bank insulation layer on the thin-film transistor configured to expose the first electrode so as to define an emission area, an organic light-emitting layer provided on the first electrode, and a second electrode configured to cover the organic light-emitting layer. The source or drain electrode includes a plurality of layers and the first electrode is integrally formed with any one layer portion of the source or drain electrode.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a first die vertically over the substrate, a second die vertically over the substrate and laterally separated from the first die with a gap, and an insulation material in the gap. The substrate is at least partially overlapped with the gap when viewed from a top view perspective, and a Young's modulus of the substrate is higher than that of the insulation material.

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.

Abstract: The disclosure provides a pixel circuit for driving a light emitting diode. A second terminal of a driving transistor is coupled to a first terminal of the light emitting diode, and a control terminal of the driving transistor receives a bias voltage. A coupling switch is coupled between a first terminal and the control terminal of the driving transistor and controlled by a first selection signal to be turned on or off. A first terminal of a first switch receives a display data voltage or a reference voltage, and the first switch is controlled by a second selection signal to be turned on or off. A first terminal of a second switch is coupled to a second terminal of the first switch. A second terminal of the second switch is coupled between the second terminal of the driving transistor and the light emitting diode, and the second switch is controlled by the first selection signal to be turned on or off.

Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Abstract: A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Abstract: Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.

Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Abstract: An organic light emitting display device includes a substrate including a white pixel region, a blue color filter pattern in a first region of the white pixel region, an overcoat layer covering the blue color filer pattern and including a micro-lens, a first electrode on the overcoat layer, an organic emitting layer covering the first electrode, and a second electrode covering the organic emitting layer.

Abstract: An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality of conductive pads. The conductive vias contacts the conductive pads respectively. The alignment mark is disposed on the die and spaced apart from the conductive vias. The insulating encapsulation encapsulates the die and contacts side surfaces of the conductive vias and the alignment mark.

Abstract: A method for manufacturing an electronic device, according to the present disclosure, may include: detecting positions of one or more heat sources, which are disposed in a printed circuit board or in a display of the electronic device, or a path of the heat that is diffused from the heat sources; selecting a heat radiating structure to correspond to the positions of the heat sources or the diffusion path; selecting an adiabatic member or a heat radiating member, which is disposed based the selected heat radiating structure to block or radiate the heat transferred from the heat source; and forming the selected heat radiating structure or disposing the selected adiabatic member or heat radiating member on the periphery of the heat source or on the diffusion path.

Abstract: A battery box structure includes: a box body, inside thereof having first and second accommodation spaces, two ends of the first accommodation space and two ends of the second accommodation space respectively configured with first positive and first negative conductors and second positive and second negative conductors, bottoms of the first positive, first negative, second positive and second negative conductors respectively passed through the box body and extended out to form first, second, third and fourth terminals, the second terminal having a groove, one side of the groove extended with an engagement portion, the first positive conductor in electric connection with the second negative conductor, the third terminal in combination with a press rod positioned above the groove, and the press rod spaced apart from the groove a preset distant; and a light emitting element, respectively in combination with the first and fourth terminals.

Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.