Patents by Inventor Jung Chen

Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170299
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
  • Publication number: 20240170415
    Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.
    Type: Application
    Filed: April 11, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240168329
    Abstract: An electronic device including a first light emitting unit, a second light emitting unit, a first optical layer and a second optical layer is disclosed. The first light emitting unit emits a first light. The second light emitting unit emits a second light. At least one of the first light and the second light passes through the first optical layer. The second optical layer is overlapped with the first optical layer. The second optical layer is configured to scatter the first light emitted from the first light emitting unit. When the first light emitting unit emits the first light, the second light emitting unit selectively emits the second light.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: InnoLux Corporation
    Inventors: Kuei-Sheng CHANG, Kuo-Jung Wu, Po-Yang Chen, I-An Yao
  • Patent number: 11988559
    Abstract: A color calibrator includes a first casing, a second casing and an optical sensor. The first casing has an accommodating recess and a plurality of first positioning members, wherein the first positioning members are arranged along an axial direction of the accommodating recess. The second casing is telescopically disposed in the accommodating recess. The second casing has a second positioning member. One of the first positioning member and the second positioning member is a magnet. Another one of the first positioning member and the second positioning member is a magnet or a magnetic induction material. The second positioning member cooperates with one of the first positioning members to position the second casing at one of a plurality of telescopic positions with respect to the first casing. The optical sensor is disposed on the second casing.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 21, 2024
    Assignee: Qisda Corporation
    Inventors: Chun-Jung Chen, Yung-Yeh Chang
  • Patent number: 11988246
    Abstract: An axial-rotation locking-mechanism assembly includes a handle, a locking assembly, and a shaft. The locking assembly includes a locking element and a cam mechanism. The shaft is operatively connected to the handle and the locking assembly. When the handle is rotated in a first direction, the shaft is rotated in a first direction and drives the cam mechanism to move the locking element in a first axial direction. When the handle is rotated in a second direction, the shaft is rotated in a second direction and drives the cam mechanism to move the locking element in a second axial direction. The second direction is the opposite of the first direction. The first axial direction is the opposite of the second direction.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 21, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Wei Lin, Che-Hung Lin
  • Patent number: 11991867
    Abstract: A closed-loop liquid cooling system includes a liquid coolant conduit, a cold plate, a pump and a heat exchanger. The liquid coolant conduit is in proximity to a heat-generating electrical component. The liquid coolant conduit allows circulation of a liquid coolant to extract heat therefrom. The liquid coolant conduit includes an inner portion that surrounds and contains the liquid coolant, and an outer portion configured to prevent or inhibit leakage of the liquid coolant from the inner portion and also detect any leakage from the inner portion. The cold plate is in thermal communication with the liquid coolant. The pump is configured to transport the liquid coolant in the liquid coolant conduit. The heat exchanger is coupled to the liquid coolant conduit to extract heat therefrom.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: May 21, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yu-Nien Huang, Jen-Mao Chen, Shao-Yu Chen
  • Patent number: 11990507
    Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11991853
    Abstract: A clip for securing one or more cables associated with a computing device includes a baseplate, a first wall, and a second wall. The first wall and the second wall extend from the baseplate. The first wall has a first inward projection at a distal end thereof. The second wall has a second inward projection at a distal end thereof. The first wall is generally parallel to the second wall. The first wall and the second wall are spaced apart from each other by an interior space configured to receive the one or more cables. The first inward projection and the second inward projection aid in preventing the one or more cables from moving outside of the interior space.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: May 21, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Wei Lin, Jui-Chung Lee, Hui-Ying Suk
  • Publication number: 20240164054
    Abstract: A single-phase immersion cooling system includes an immersion cooling tank having a component area, which is separate from a main chamber and is configured to receive a heat-generating electronic device. A coolant circulates along a flow path, in a chamber path through the main chamber and a component path through the component area. A rotating propeller is mounted within the immersion cooling tank, causing a driven flow path in the component area. The driven flow path is configured to cause contact between the coolant in the driven flow path and the heat-generating electronic device when the heat-generating electronic device is received within the component area. The coolant in the driven flow path circulates at a faster speed than the coolant in the chamber path.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 16, 2024
    Inventors: Chao-Jung CHEN, Yu-Nien HUANG, Chang-Yu CHIANG
  • Patent number: 11983052
    Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 14, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
  • Publication number: 20240150534
    Abstract: A polyethylene terephthalate composite material containing glass fiber and a method for manufacturing the same are provided. The polyethylene terephthalate composite material includes 40 to 65.5 parts by weight of polyethylene terephthalate, 5 to 40 parts by weight of the glass fiber, and 0.15 to 2.5 parts by weight of a crystallizing agent. The crystallizing agent includes an inorganic crystallizing agent and an organic crystallizing agent, and an added amount of the inorganic crystallizing agent is less than an added amount of the organic crystallizing agent.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 9, 2024
    Inventors: TE-CHAO LIAO, HAN-CHING HSU, CHUN-LAI CHEN, Jui-Jung Lin
  • Publication number: 20240150532
    Abstract: A prepreg and uses thereof are provided. The prepreg includes an organic fiber woven fabric impregnated or coated with a thermally curable resin composition, wherein the thermally curable resin composition includes: (A) a polyphenylene ether resin having an unsaturated functional group; (B) a polyfunctional vinyl aromatic copolymer; and (C) a compound having the structure of formula (I), wherein, in formula (I), X is a C1-C10 linear or branched alkylene; and the polyfunctional vinyl aromatic copolymer is prepared by copolymerizing one or more divinyl aromatic compounds with one or more monovinyl aromatic compounds.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 9, 2024
    Inventors: Wei-Jung YANG, Meng-Huei CHEN
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240145302
    Abstract: A semiconductor device and a method for manufacturing an interconnecting metal layer thereof are provided. The semiconductor device includes a gate layer, a dielectric layer, an insulating layer, an epitaxial layer, and a sidewall liner. The dielectric layer is disposed on one side of the gate layer, the insulating layer is disposed on another side of the gate layer, the epitaxial layer is located on the insulating layer, and the sidewall liner penetrates the dielectric layer and the gate layer, and one end of the sidewall liner is connected to the epitaxial layer. The sidewall liner is converted from a high-k material to a low-k material by hydrogen and oxygen plasma treatments.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shien SHIAH, Bor Chiuan HSIEH, Tsai-Jung HO, Meng-Ku CHEN, Tze-Liang LEE
  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240145990
    Abstract: A connector includes a base, a latch, and a first axle element. The latch is disposed on the base. The latch includes a main portion, a front-left arm, a front-right arm, a back-left arm, and a back-right arm, wherein each of the front end of the front-left arm and the front end of the front-right arm has a hook-shaped structure, and each of the back-left arm and the back-right arm has a hole. The first axle element is pivoted to the hole of the back-left arm and the base. The back-left arm of the latch is located along the lengthwise direction of the front-left arm, and the back-left arm and the front-left arm are connected by a connecting structure.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 2, 2024
    Inventors: Yi-Hsing CHUNG, Shi-Jung CHEN, Chih-Wen FAN
  • Publication number: 20240145403
    Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240145249
    Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.
    Type: Application
    Filed: March 24, 2023
    Publication date: May 2, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Gang CHEN, Wan Chen HSIEH, Bo-Cyuan LU, Tai-Jung KUO, Kuo-Shuo HUANG, Chi-Yen TUNG, Tai-Chun HUANG
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung