Abstract: A fan brake structure includes a fan and a brake device. The fan has a frame body, a fan impeller and a stator. The brake device is disposed under a bottom of a bearing cup. The brake device has a driving member, a brake member and an elastic member. The elastic member abuts against one end of the brake member. The other end of the brake member has a boss body. The driving member has a spiral rail. When the driving member rotates, the boss body moves along the spiral rail, whereby the brake member linearly reciprocally moves upward to brake the fan impeller or linearly reciprocally moves downward to release the fan impeller from the braking.

Abstract: A fan braking structure includes a fan including a frame having an upright bearing cup, and a fan impeller having a vertical rotating shaft pivotally received in the bearing cup and provided at a free end with a groove; a braking structure located at a lower part of the bearing cup and including a brake plate and an electromagnet, and the brake plate being provided at one side with a protruded brake pin and at another side with a magnetic member; and an elastic element disposed between and pressed against the brake plate and the electromagnet. When the fan is powered off, the electromagnet is energized and produces magnetic poles that magnetically repel the magnetic member, such that the brake pin is pushed by a magnetic force and the elastic element toward the rotating shaft to engage with the groove, causing the fan to brake and stop rotating inertially.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: The present disclosure relates to an integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Abstract: A module comprises a tray, a mechanical switch, and a linkage system. The tray is configured to receive a circuit board thereon. The mechanical switch is mounted to the tray and movable between an unsecured position and a secured position. The linkage system is mechanically coupled to the mechanical switch, and moves between an unsecured configuration and a secured configuration in response to the mechanical switch moving between the unsecured position and the secured position. When the module is coupled to a computing device and the linkage system is in the secured configuration, the linkage system engages the computing device, such that the module is locked to the computing device. When the module is coupled to the computing device and the linkage system is in the unsecured configuration, the linkage system is disengaged from the computing device, such that the module is unlocked from the computing device.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: An electronic device includes a first substrate and a second substrate stacked on each other, a plurality of pad groups, a plurality of channels, and a plurality of conductive members. The first substrate and the second substrate respectively have an inner surface facing to each other and an outer surface away from each other. Each pad group includes two conductive pads, which are respectively disposed at the outer surfaces of the first substrate and the second substrate and are located corresponding to each other. The channels pass through the first substrate and the second substrate, and each channel is disposed corresponding to one of the pad groups. Two ends of each channel are respectively sealed by the two conductive pads of the corresponding pad group. The conductive members are disposed in the channels, and each conductive member is electrically connected to the two conductive pads of the corresponding pad group.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: A fan guard for a fan container includes a housing and a plurality of wings. The housing has a hollow interior defined by a cylindrical inner surface. The housing extends longitudinally between a first housing end and a second housing end. The plurality of wings is positioned within the hollow interior of the housing. Each wing of the plurality of wings extends radially, from a center of symmetry of the cylindrical inner surface to the cylindrical inner surface. Each wing of the plurality of wings is radially curved between the first housing end and the second housing end.

Abstract: A lamp structure of an umbrella contains a body, an illumination device, and a control pusher. The body includes a shaft, a notch, a runner slidably, and multiple stretchers. The illumination device includes at least one lighting element, a circuit board, and a battery. The circuit board has a control switch, when the runner is moved upward to push the illumination device, the umbrella is opened. The control pusher is connected to the runner and includes a controlling element. The control pusher is slid vertically with respect to the shaft and is switched in three-section positions, such that the control pusher is slid to a first position, a second position, and a third position relative to the shaft to drive the control switch to be conducted or not so that the circuit board controls the at least one lighting element to power on or off.

Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A display device including a first light emitting unit, a second light emitting unit, a first optical layer and a second optical layer is disclosed. The first optical layer is disposed on at least one of the first light emitting unit and the second light emitting unit, and the first optical layer includes a collimating layer. The second optical layer is disposed on the first light emitting unit. The second optical layer is configured to scatter a first light emitted from the first light emitting unit but does not scatter a second light emitted from the second light emitting unit.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: Disclosed is a cable end connector. The cable end connector includes: a base; a circuit board fixedly disposed in the base; a cable connected to the circuit board; and a latch fixedly disposed in a mounting groove of the base. The latch has a body portion and a bent portion formed by bending downwards from a rear edge of the body portion, the bent portion can abut against the base, and the body portion has a plurality of hooks extending forwards. The cable end connector further includes a connecting shaft, a mounting space for the connecting shaft to penetrate through is formed between the body portion and the bent portion, and the connecting shaft penetrates through the mounting space and is inserted into a connecting hole of the base, which can prevent the latch from falling off and has better connection reliability.