Patents by Inventor Jung-Chih Tsao

Jung-Chih Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083278
    Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Chi-Ming LU, Chih-Hui HUANG, Sheng-Chan LI, Jung-Chih TSAO, Yao-Hsiang LIANG
  • Patent number: 10510798
    Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Chih-Chang Huang, Ching-Ho Hsu
  • Patent number: 10475847
    Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Sheng-Chan Li, Jung-Chih Tsao, Yao-Hsiang Liang
  • Publication number: 20190148442
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: CHIH-CHANG HUANG, CHI-MING LU, JIAN-MING CHEN, JUNG-CHIH TSAO, YAO-HSIANG LIANG
  • Publication number: 20190043915
    Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 7, 2019
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Chih-Chang Huang, Ching-Ho Hsu
  • Publication number: 20190019743
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming a recess extending between the first side and the second side; and disposing a conductive material in the recess to form a conductive via, wherein the conductive via includes an interface, a first portion adjacent to the first side and a second portion adjacent to the second side, the interface is disposed between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: LI-YEN FANG, CHIH-CHANG HUANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
  • Patent number: 10157953
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Huang, Chi-Ming Lu, Jian-Ming Chen, Jung-Chih Tsao, Yao-Hsiang Liang
  • Patent number: 10134801
    Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Chih-Chang Huang, Ching-Ho Hsu
  • Publication number: 20180261547
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed on the substrate, and a conductive stack disposed within the dielectric layer. The conductive stack includes at least one first conductive layer, a second conductive layer disposed over the at least one first conductive layer, and a contact structure disposed between the at least one first conductive layer and the second conductive layer. The contact structure includes a contact via electrically connecting the at least one first conductive layer to the second conductive layer, and a glue layer conformal to sidewalls and a bottom surface of the contact via. The glue layer has isolated lattices and an amorphous region at which the isolated lattices are uniformly distributed.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 13, 2018
    Inventors: Chi-Ming LU, Jung-Chih TSAO, Yao-Hsiang LIANG, Chih-Chang HUANG, Han-Chieh HUANG
  • Patent number: 10074594
    Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Li-Yen Fang, Chih-Chang Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9991204
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9859124
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate with a dielectric disposed thereon, wherein the dielectric has a recess formed by a plurality of exposed surfaces; forming a conductive film on the plurality of exposed surfaces; applying a surface agent to the recess so that the surface agent adheres to a portion of the conductive film; immersing the substrate into an electroplating solution comprising metallic ions; and applying a bias to the conductive film in order to fill metallic material in the recess.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9847296
    Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chung Chang, Jung-Chih Tsao, Chun Che Lin, Yu-Ming Huang, Tain-Shang Chang, Jian-Shin Tsai
  • Publication number: 20170323940
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20170317134
    Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 2, 2017
    Inventors: Chi-Ming LU, Chih-Hui HUANG, Sheng-Chan LI, Jung-Chih TSAO, Yao-Hsiang LIANG
  • Publication number: 20170294473
    Abstract: Some embodiments of the present disclosure provide a back side illuminated. (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Application
    Filed: June 15, 2017
    Publication date: October 12, 2017
    Inventors: CHIH-CHANG HUANG, CHI-MING LU, JIAN-MING CHEN, JUNG-CHIH TSAO, YAO-HSIANG LIANG
  • Publication number: 20170287841
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen FANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Yu-Ku LIN
  • Patent number: 9735231
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 9711454
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9691804
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Huang, Chi-Ming Lu, Jian-Ming Chen, Jung-Chih Tsao, Yao-Hsiang Liang