Patents by Inventor Jung-Chih Tsao
Jung-Chih Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170154917Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2?x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.Type: ApplicationFiled: February 19, 2016Publication date: June 1, 2017Inventors: Chi-Ming LU, Chih-Hui HUANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Chih-Chang HUANG, Ching-Ho HSU
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Publication number: 20170062343Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.Type: ApplicationFiled: August 29, 2015Publication date: March 2, 2017Inventors: Li-Yen FANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Yu-Ku LIN
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Publication number: 20160307952Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: CHIH-CHANG HUANG, CHI-MING LU, JIAN-MING CHEN, JUNG-CHIH TSAO, YAO-HSIANG LIANG
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Publication number: 20160307823Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: LI-YEN FANG, CHIH-CHANG HUANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
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Publication number: 20160307761Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate with a dielectric disposed thereon, wherein the dielectric has a recess formed by a plurality of exposed surfaces; forming a conductive film on the plurality of exposed surfaces; applying a surface agent to the recess so that the surface agent adheres to a portion of the conductive film; immersing the substrate into an electroplating solution comprising metallic ions; and applying a bias to the conductive film in order to fill metallic material in the recess.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: LI-YEN FANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
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Publication number: 20150279838Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
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Publication number: 20150235954Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chung Chang, Jung-Chih Tsao, Chun Che, Yu-Ming Huang, Tain-Shang Chang, Jian-Shin Tsai
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Publication number: 20150235953Abstract: A semiconductor device and method of formation are provided. A semiconductor device includes a copper fill over a first layer in a first opening. The first layer includes cobalt and tungsten. A third layer including cobalt and tungsten is over the copper fill and the first layer. The first layer including cobalt and tungsten has a smoother sidewall than a first layer that does not have cobalt or tungsten. A smoother sidewall decreases defects in the copper fill, thus increasing conductivity of the copper fill. The first layer and the third layer reduce out diffusion of copper from the copper fill as compared to a semiconductor device that does not comprise such layers.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Shih-Chieh Chang, Wen-Hsi Lee, Ying-Lang Wang
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Patent number: 8552529Abstract: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.Type: GrantFiled: June 5, 2012Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Chih Tsao, Yu-Sheng Wang, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 8531036Abstract: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.Type: GrantFiled: July 31, 2012Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Jung-Chih Tsao, Yu-Sheng Wang
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Publication number: 20120292768Abstract: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.Type: ApplicationFiled: July 31, 2012Publication date: November 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Jung-Chih Tsao, Yu-Sheng Wang
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Publication number: 20120241908Abstract: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.Type: ApplicationFiled: June 5, 2012Publication date: September 27, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Jung-Chih TSAO, Yu-Sheng WANG, Kei-Wei CHEN, Ying-Lang WANG
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Patent number: 8247322Abstract: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.Type: GrantFiled: March 1, 2007Date of Patent: August 21, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Jung-Chih Tsao, Yu-Sheng Wang
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Patent number: 7969708Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.Type: GrantFiled: November 1, 2007Date of Patent: June 28, 2011Assignee: Taiwan Semiconductor Company, Ltd.Inventors: Jung-Chih Tsao, Miao-Cheng Liao, Phil Sun, Kei-Wei Chen
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Publication number: 20100230815Abstract: Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chih Tsao, Kei-Wei Chen, Yu-Ku Lin
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Patent number: 7667835Abstract: An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.Type: GrantFiled: August 28, 2006Date of Patent: February 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsi-Kuei Cheng, Jung-Chih Tsao, Hsien-Ping Feng, Ming-Yuan Cheng, Steven Lin, Ray Chuang
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Publication number: 20090116169Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Inventors: Jung-Chih Tsao, Miao-Cheng Liao, Phil Sun, Kei-Wei Chen
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Patent number: 7481910Abstract: A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.Type: GrantFiled: June 30, 2004Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Ping Feng, Ming-Yuang Cheng, Si-Kwua Cheng, Steven Lin, Jung-Chih Tsao, Chen-Peng Fan, Chi-Wen Liu
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Publication number: 20080251889Abstract: A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chih Tsao, Yu-Sheng Wang, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 7432192Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.Type: GrantFiled: February 6, 2006Date of Patent: October 7, 2008Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu