Abstract: A semiconductor substrate includes a plurality of gate electrodes crossing active patterns on a substrate and extending in a second direction, the gate electrodes spaced apart in the second direction from each other, a gate separation pattern having a major axis in the first direction and between two of the gate electrodes, the two of the gate electrodes adjacent to each other in the second direction, and a plurality of gate spacers covering sidewalls of respective ones of the gate electrodes, the gate spacers crossing the gate separation pattern and extending in the second direction. The gate separation pattern includes a lower portion extending in the first direction, an intermediate portion protruding from the lower portion and having a first width, and an upper portion between two adjacent gate spacers and protruding from the intermediate portion, the upper portion having a second width less than the first width.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.

Abstract: The present invention relates to a cathode active material for a lithium secondary battery, and more particularly, to a cathode active material for a lithium secondary battery, which includes a core portion and a shell portion surrounding the core portion, in which a total content of cobalt in the core portion and the shell portion is 5 to 12 mol %, and the content of cobalt in the core portion and the shell portion is adjusted to be within a predetermined range. In the cathode active material precursor and the cathode active material for a secondary battery prepared using the same according to the present invention, optimal capacity of a lithium secondary battery may be increased by adjusting the cobalt content in the particles of the cathode active material, and life characteristics may be enhanced by improving stability.

Abstract: The present invention relates to a cathode active material composition for a lithium secondary battery and a lithium secondary battery including the same, and more particularly, to a cathode active material composition for a lithium secondary battery, including a mixture of particles which are different in Ni composition and size and prepared at the same heat treatment temperature, and a lithium secondary battery including the same. According to the present invention, optimal capacity manifestation temperatures of a coarse particle and a fine particle may be adjusted to be similar by adjusting an Ni content of the coarse particle and the fine particle, and thus, a lithium secondary battery having enhanced output and lifetime may be manufactured.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A circuit board includes an insulating part including insulating layers, metal layers disposed on the insulating layers, vias each passing through at least one insulating layer among the insulating layers and connecting together at least two metal layers among the metal layers; a first thermally conductive structure including a thermally conductive material, at least a part of the thermally conductive structure being inserted into the insulating part, a first via having one surface contacting the first thermally conductive structure, a first metal pattern contacting another surface of the first via, a first bonding member connected to the first metal pattern, and pads to which a first electronic component is connected on an outermost surface of a metal layer disposed on an outermost surface of the insulating part, the pads being at least in a first region and a second region having a higher temperature than the first region.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.

Abstract: A self capacitance type touch panel includes a touch driver including a plurality of touch ICs; and a touch unit including a plurality of touch groups that are controlled by the plurality of touch ICs, respectively, wherein each of the plurality of touch groups includes a plurality of pattern electrodes, and some touch ICs selected from the plurality of touch ICs apply sensing voltages to respective corresponding touch groups at a same timing.

Abstract: A printed circuit board and a manufacturing method thereof are provided. A printed circuit board may include a first insulating layer comprising a photosensitive material on a core layer, a second insulating layer comprising a material comprising a reinforcing material on the first insulating layer, and a cavity formed in the first insulating layer and the second insulating layer.

Abstract: Provided are a display device and a touch sensing method of a display device. The display device includes a timing controller temporally dividing one frame period and driving a display panel such that a display mode for displaying an image in the display panel and a touch mode for sensing a user's touch are alternately driven, and a touch sensing unit detecting the user's touch with a touch raw data difference between adjacent touch sensing blocks in the touch mode. In the display mode, the touch sensing unit generates a display compensation value for compensating for an error of the touch raw data due to a differential of display data applied to the adjacent touch sensing blocks to detect the user's touch.

Abstract: A display device including a touch screen and method of driving the same are provided. In a method of driving display device including a touch screen, the display device including a panel including a plurality of gate lines, and a plurality of electrodes respectively corresponding to the plurality of gate lines, the method includes: applying, by a display driving unit, a gate signal to a subset of the plurality of gate lines, applying, by a touch sensing unit: a common voltage to a first subset of the plurality of electrodes corresponding to the subset of the plurality of gate lines, and the touch scan signal to a second subset of the plurality of electrodes, other than the first subset of the plurality of electrodes.

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.