Abstract: A system and method for time synchronization on a network is provided. According to the system and method for time synchronization, a slave clock device does not continuously receive a time synchronization message periodically transferred from a master clock device and thus does not correct its time upon all such occasions. Rather, the slave clock device requests time information from the master clock device only when the slave clock device needs to correct its time, and receives a time synchronization message transferred from the master clock device and compensates for its time deviation only while the slave clock device is activated, thereby reducing its power consumption and amount of computation.

Abstract: Provided are a method and apparatus for dynamically managing hierarchical flows that more efficiently process packet traffic while maintaining compatibility with an existing packet data network in transferring both circuit traffic and packet traffic in a packet switched network. The method for dynamically managing hierarchical flows includes: receiving data packets, classifying the data packets according to attributes of the received data packets, and producing first flows; determining whether traffic of each of the first flows exceeds a predetermined bandwidth limit, and performing a packet drop process or producing second flows for first flows that exceed the bandwidth limit, according to a flow-specific policy; and performing second flow processing on the second flows according to a second flow policy. Only flows exceeding the bandwidth limit or causing congestion are hierarchically divided for management. This makes it possible to finely manage the flows without complex operations.

Abstract: A liquid crystal display device having a digitizer and a method for fabricating the same are disclosed in the present invention. The liquid crystal display device includes a liquid crystal display device module, a printed circuit board located in close proximity to a support main of the liquid crystal display device module, and a fixing device to insert a digitizer.

Abstract: A nitride based hetero-junction field effect transistor includes a high resistance nitride semiconductor layer formed on a substrate, an Al-doped GaN layer formed on the high resistance nitride semiconductor layer and having an Al content of 0.1˜1%, an undoped GaN layer formed on the Al-doped GaN layer, and an AlGaN layer formed on the undoped GaN layer such that a two-dimensional electron gas (2DEG) layer is formed at an interface of the undoped GaN layer.

Abstract: Disclosed is a fiber reinforced plastic wire used as the overhead transmission cable. The fiber reinforced plastic wire for a strength member of an overhead transmission cable according to the present invention includes a wire having a predetermined diameter and composed of thermoset matrix resin; and a plurality of high strength fibers dispersed parallel to a longitudinal direction in an inside of the wire, the high strength fibers being surface-treated with a coupling agent to improve interfacial adhesion to the matrix resin. The fiber reinforced plastic wire of the present invention has the high tensile strength at the room temperature and the high temperature since its high strength fiber is surface-treated with a coupling agent. The fiber reinforced plastic wire can be also effectively used as the strength member in the overhead transmission cable since it has the excellent low coefficient of thermal expansion, etc. and is light-weight.

Abstract: A process for preparing a nitride based semiconductor device in accordance with the present invention comprises growing a high temperature AlN single crystal layer on a substrate; growing a first GaN layer on the high temperature AlN single crystal layer in a first V/III ratio, under a first pressure of 300 Torr or more, such that the predominant direction of growth is the lateral direction; and growing a second GaN layer on the first GaN layer in a second V/III ratio lower than the first V/III ratio, under a second pressure lower than the first pressure such that the predominant direction of growth is the lateral direction.

Abstract: A process for preparing a nitride based semiconductor device in accordance with the present invention comprises growing a high temperature AlN single crystal layer on a substrate; growing a first GaN layer on the high temperature AlN single crystal layer in a first V/III ratio, under a first pressure of 300 Torr or more, such that the predominant direction of growth is the lateral direction; and growing a second GaN layer on the first GaN layer in a second V/III ratio lower than the first V/III ratio, under a second pressure lower than the first pressure such that the predominant direction of growth is the lateral direction.

Abstract: Provided is a nitride-based semiconductor device in which a SAW filter and a HFET are integrated on a single substrate, as well as a method for manufacturing the same. The nitride-based semiconductor device comprises a semi-insulating GaN layer formed on a substrate, a plurality of electrodes for a SAW filter formed on one side of the semi-insulating GaN layer, an Al-doped GaN layer formed on the other side of the semi-insulating GaN layer, an AlGaN layer formed on the Al-doped GaN layer, and a plurality of electrodes for an HFET formed on the AlGaN layer. Both sides of the semi-insulating GaN layer have the same surface level.

Abstract: A matrix-type display device having a repair layout, particularly, a matrix-type display device which can be repaired in a pixel unit, is provided. Two or more of signal lines such as scanning signal lines, displaying signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the displaying signal lines and scanning signal lines, the short of the pixel electrode and signal line, and the loss of electrode of a switching element, can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Abstract: Disclosed is a gate signal delay compensating LCD that comprises an LCD panel including a plurality of gate lines, a plurality of data lines insulated from and crossing the gate lines, a plurality of TFT each of which having a gate electrode connected to the gate line and a source electrode connected to the data line, a pixel electrode connected to a drain electrode of the TFT and a common electrode facing the pixel electrode, liquid crystal filled between the pixel electrode and the common electrode, and a signal delay compensator connected to ends of the gate lines to compensate for the gate signal delay; a gate driver for supplying a gate signal for turning on and off the TFT to the gate line so as to drive the LCD panel; a data driver for supplying a data voltage that represents an image signal to the data line so as to drive the LCD panel; and a signal controller connected to a signal source, the gate driver and the data driver, and processing the image signal provided by the signal source to enable the

Abstract: A device of driving a liquid crystal display including a plurality of pixels connected to gate lines and data lines and arranged in a matrix is provided. The driving device includes: a gray voltage generator (800) generating a plurality of gray voltages; an image signal modifier (600) receiving first image signals for a pixel row and second image signals for a next pixel row, selecting modified image signal depending on the first image signals and the second image signals, and outputting the modified image signals; and a data driver (500) selecting data voltages from the gray voltages based on the modified image signals from the image signal modifier and applying the data voltages to the pixels.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms a adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material to cationically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method.

Abstract: A matrix-type display capable of being repaired by pixel unit, Two or more of signal lines such as scanning lines, image signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the image signal lines and scanning lines, the short of the pixel electrode and the signal line, and the loss of electrode of a switching element, and a pixel defect can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Abstract: The present invention discloses a tracking resistant resin composition comprising: 100 weight parts of at least one selected from the group consisting of polyolefins and copolymers of different olefins; 0.1 to 1.5 weight parts of carbon black; 0.1 to 2 weight parts of a UV and light stabilizer; and 0.1 to 2 weight parts of an antioxidant and a cable using the same.

Abstract: A liquid crystal display device having a digitizer and a method for fabricating the same are disclosed in the present invention. The liquid crystal display device includes a liquid crystal display device module, a printed circuit board located in close proximity to a support main of the liquid crystal display device module, and a fixing device to insert a digitizer.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: A matrix-type display capable of being repaired by pixel unit, Two or more of signal lines such as scanning lines, image signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the image signal lines and scanning lines, the short of the pixel electrode and the signal line, and the loss of electrode of a switching element, and a pixel defect can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.