Abstract: A washing machine includes a rotary tub having a diameter progressively increasing from a first end side thereof to a second end side thereof located opposite the first end side, dehydration holes arranged at the second end side of the rotary tub, and a dehydration hole switching unit to open and close the dehydration holes. The dehydration holes are opened depending on increase of a rate of rotation of the rotary tub.

Abstract: Disclosed herein is a nitride based semiconductor device. The nitride based semiconductor device includes: a base substrate; an epitaxial growth layer disposed on the base substrate and having a defect generated due to lattice disparity with the base substrate; a leakage current barrier covering the epitaxial growth layer while filling the defect; and an electrode part disposed on the epitaxial growth layer.

Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.

Abstract: A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.

Abstract: A method of manufacturing a vertical GaN-based LED includes forming a nitride-based buffer layer on a silicon substrate; sequentially forming a p-type GaN layer, an active layer, and an n-type GaN layer on the nitride-based buffer layer; forming an n-electrode on the n-type GaN layer; forming a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed.

Abstract: A washing machine having an improved structure which increases washing capacity without increasing the size of the washing machine. The washing machine includes a cabinet including an outer part and a cylindrical inner part connected to the outer part, a spin basket rotatably disposed in the inner part and including a bottom and a side wall extending from the bottom, a pulsator rotatably disposed in the spin basket, a motor provided under the spin basket, a clutch to selectively transmit power of the motor to the spin basket or the pulsator, a base plate to fix the clutch and the motor, and suspension members connecting the base plate to the upper portion of the cabinet. Wash water is stored within the spin basket and is not stored outside the spin basket during a washing cycle.

Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.

Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.

Abstract: Provided is a data flow-parallel processing apparatus and method. The data flow-parallel processing apparatus may include a lower layer processing unit to identify a flow of inputted first data, a distribution unit to select, from among a plurality of upper layer processing units, an upper layer processing unit corresponding to the flow, and to transmit the first data to the selected upper layer processing unit, and an upper layer processing unit to process an upper layer packet of the first data, based on a local memory corresponding to the flow from among a plurality of local memories.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed. The adjuvant comprising a mixture of a linear polyelectrolyte with a graft type polyelectrolyte makes it possible to increase polishing selectivity as compared to CMP slurry using the linear polyelectrolyte alone, and to obtain a desired range of polishing selectivity by controlling the ratio of the linear polyelectrolyte to the graft type polyelectrolyte.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: An apparatus includes a difference extraction unit to extract a difference between a second time stamp value, which is obtained by adjusting a first time stamp value that is measured at a time of arrival of a synchronization message transmitted by the master at a Layer 3 to be synchronized in frequency with a clock of the master, and a third time stamp value, which is measured at a time of departure of the synchronization message from the master; a minimum filter to select a minimum from one or more difference values extracted by the difference extraction unit; and a delay variation calculation unit to estimate a time of arrival of a current synchronization message at the Layer 3 based on the selected minimum and calculate a delay variation.

Abstract: A multi-layer data processing apparatus and method are provided. The multi-layer data processing apparatus includes a lower hierarchy processing unit configured to generate at least one lower hierarchy flow from input data using lower hierarchy information, and to allocate the generated lower hierarchy flows to a plurality of lower hierarchy processors to perform lower hierarchy processing in respect of the lower hierarchy flows in parallel; and a higher hierarchy processing unit configured to generate at least one higher hierarchy flow from data transmitted from the lower hierarchy processing unit using higher hierarchy information, and to allocate the generated higher hierarchy flows to a plurality of higher hierarchy processors to perform higher hierarchy processing in parallel in respect of the higher hierarchy flows.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged material in order to increase polishing selectivity of the anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed.

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract: Disclosed is an adjuvant for controlling polishing selectivity when polishing a cationically charged material simultaneously with an anionically charged material. CMP slurry comprising the adjuvant is also disclosed. The adjuvant comprises: (a) a polyelectrolyte that forms an adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material; (b) a basic material; and (c) a fluorine-based compound. when the adjuvant for controlling polishing selectivity of CMP slurry according to the present invention is applied to a CMP process, it is possible to increase the polishing selectivity of a silicon oxide layer, to obtain a uniform particle size of CMP slurry, to stabilize variations in viscosity under an external force and to minimize generation of microscratches during a polishing process.

Abstract: An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.

Abstract: Disclosed herein is a nitride-based semiconductor device. The nitride-based semiconductor device includes a base substrate having a PN junction structure, an epi-growth layer disposed on the base substrate, and an electrode unit disposed on the epi-growth layer.

Abstract: The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

Abstract: An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.