Patents by Inventor Jung-hun Seo

Jung-hun Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160204306
    Abstract: Light-emitting devices having a multiple quantum well (MQW) pin diode structure and methods of making and using the devices are provided. The devices are composed of multilayered semiconductor heterostructures. The devices include one or more interfacial layers of a material that allows current tunneling through lattice mismatched heterogeneous junctions at the interfaces between the intrinsic active region and the p-type and/or n-type doped charge injection layers.
    Type: Application
    Filed: October 6, 2014
    Publication date: July 14, 2016
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Patent number: 9337622
    Abstract: Ultra compact DBRs, VCSELs incorporating the DBRs and methods for making the DBRs are provided. The DBRs are composed of a vertical reflector stack comprising a plurality of adjacent layer pairs, wherein each layer pair includes a layer of single-crystalline Group IV semiconductor and an adjacent layer of silicon dioxide.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 10, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Publication number: 20160097145
    Abstract: Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 7, 2016
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Publication number: 20160060759
    Abstract: A gas injection apparatus, which can sequentially supply a substrate with at least two kinds of source gases reacting with each other in a container, and thin film deposition equipment including the gas injection apparatus, are provided. The gas injection apparatus includes a base plate, a first gas supply region protruding from the base plate, a second gas supply region protruding from the base plate and adjacent the first gas supply region, and a trench defined by a sidewall of the first gas supply region and a sidewall of the second gas supply region. The sidewall of the first gas supply region and the sidewall of the second gas supply region face each other and extend in a radial direction on the base plate.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Ki-Chul Kim, Jung-Il Ahn, Jung-Hun Seo, Jong-Cheol Lee, Kyu-Hee Han, Seung-Han Lee, Jin-Pil Heo
  • Publication number: 20160020582
    Abstract: Ultra compact DBRs, VCSELs incorporating the DBRs and methods for making the DBRs are provided. The DBRs are composed of a vertical reflector stack comprising a plurality of adjacent layer pairs, wherein each layer pair includes a layer of single-crystalline Group IV semiconductor and an adjacent layer of silicon dioxide.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Patent number: 9058993
    Abstract: The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: June 16, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Xudong Wang, Zhenqiang Ma, Fei Wang, Jung-Hun Seo
  • Patent number: 9006785
    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
  • Patent number: 8866154
    Abstract: Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Publication number: 20140264375
    Abstract: Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Publication number: 20140209977
    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
  • Publication number: 20140134793
    Abstract: The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.
    Type: Application
    Filed: May 13, 2013
    Publication date: May 15, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Xudong Wang, Zhenqiang Ma, Fei Wang, Jung-Hun Seo
  • Patent number: 8502218
    Abstract: The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: August 6, 2013
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Xudong Wang, Zhenqiang Ma, Fei Wang, Jung-Hun Seo
  • Patent number: 8366827
    Abstract: Disclosed are chamber inserts and apparatuses using the chamber inserts. A chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, a first protruding portion extending outwardly from a first portion of the cylindrical body portion, the first portion positioned circumferentially along the cylindrical body portion and a second protruding portion extending outwardly from a second portion of the cylindrical body portion, the second portion positioned circumferentially along less than all of the cylindrical body portion. In another example, the chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, the cylindrical body portion including a slit and at least one hole, the slit and the at least one hole positioned circumferentially along the cylindrical body portion and a first protruding portion extending outwardly from a first portion of the cylindrical body portion.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Jin-Gi Hong, Kyung-Bum Koo, Yun-Ho Choi, Eun-Taeck Lee, Hyun Chul Kwun
  • Publication number: 20110220887
    Abstract: The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 15, 2011
    Applicant: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Xudong Wang, Zhenqiang Jack Ma, Fei Wang, Jung-Hun Seo
  • Patent number: 7902090
    Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Young-Wook Park, Jin-Gi Hong
  • Publication number: 20110053329
    Abstract: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.
    Type: Application
    Filed: November 4, 2010
    Publication date: March 3, 2011
    Inventors: Jung-Hun Seo, Hyun-Young Kim, Jin-Gi Hong
  • Patent number: 7820244
    Abstract: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Jin-Gi Hong, Yun-Ho Choi, Hyun-Chul Kwun, Eun-Taeck Lee, Jin-Ho Kim
  • Patent number: 7547632
    Abstract: A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: June 16, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Gil-Heyun Choi, Jong-Myeong Lee, Hee-Sook Park
  • Publication number: 20090011595
    Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
    Type: Application
    Filed: September 17, 2008
    Publication date: January 8, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hun SEO, Young-Wook PARK, Jin-Gi HONG
  • Patent number: 7439192
    Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Young-Wook Park, Jin-Gi Hong