Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

Abstract: Provided are a lift pin capable of preventing aluminum from depositing on the lift pin when depositing a metallic layer on a wafer through chemical vapor deposition. a system using the lift pin, and a method of manufacturing the same. The lift pin is made of stainless steel and is oxidized at a predetermined temperature for a predetermined time, such that the lift pin is not deposited with aluminum during a CVD process. Since the CVD vacuum processing chamber utilizes the heater and the lift pin which are made of oxidized SUS material, aluminum does not deposit on the heater and the lift. Therefore, when the lift pin is lowered, the lift pin is not lowered by its own weight, thereby preventing a wafer from being broken. Also, the lift pin is prevented from being ruptured by a robot moving in and out of an opening of the CVD vacuum processing chamber.

Abstract: In one embodiment, a chemical vapor deposition (CVD) apparatus comprising a plurality of backside gas (BSG) passages that pass through a heater table that controls a temperature of a plurality of local areas on a wafer and a method of forming a thin layer using the CVD apparatus are provided. The heater table comprises a wafer supporting area divided into a plurality of local areas that correspond to the local areas of the wafer. Each of the BSG passages has a BSG outlet that supplies the BSG, heated by a heater, to the local areas. Flow controllers control the flow through each of the BSG passages, thereby controlling the temperature of local areas.

Abstract: A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.

Abstract: Semiconductor devices and methods of forming a contact in semiconductor devices are provided. A semiconductor substrate is provided with a cell array region and a peripheral circuit region. A polysilicon layer is formed on the semiconductor substrate in the peripheral circuit region. A metal layer is formed on the polysilicon layer. A metal pattern is formed by removing a portion of the metal layer. The metal pattern is annealed to form a local silicide region in the polysilicon layer. A capacitor is formed on the semiconductor substrate in the cell array region after the local silicide region is formed in the polysilicon layer.

Abstract: A conductive structure is formed in an integrated circuit device by forming a lower conductive pattern on a substrate. A barrier metal layer is formed on the lower conductive pattern. The barrier metal layer is flushed with a gas that includes a halogen group gas and an upper conductive layer is formed on the barrier metal layer.

Abstract: A conductive pattern can be formed in a mold layer by removing a portion of a barrier layer outside an intaglio pattern in a mold layer to expose an upper surface of the mold layer and avoiding removing a portion of the barrier layer on the intaglio pattern. A conductive layer can be formed on the portion of the barrier layer on the intaglio pattern and on the upper surface of the mold layer. The conductive layer can be removed from the upper surface of the mold layer.

Abstract: Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.

Abstract: A method for forming a metal wiring layer of a semiconductor device, where a first layer having a recess region is formed on a semiconductor substrate. A second layer is formed on inner walls of the recess region and on an upper portion of the first layer. A third layer is formed on the second layer so as to have a smaller third layer thickness on the inner walls of the recess region than on the upper portion of the first layer. A fourth layer is then formed on the-third layer, providing a metal wiring layer with improved step coverage.

Abstract: A recess is formed in a microelectronic substrate, and then a metal-containing layer is formed that conforms to an inner surface of the recess and to a surface of the substrate adjacent the recess. A carbon concentration in a portion of the metal-containing layer on the surface of the substrate adjacent the recess is decreased in comparison to a portion of the metal-containing layer within the recess, e.g., using a plasma treatment that has a greater effect on the surface outside of the recess. Aluminum is then deposited on the metal-containing layer to form an aluminum layer that conforms to the inner surface of the recess and to the surface of the substrate adjacent the recess. Preferably, the carbon concentration in the portion of the metal-containing layer within the recess is sufficiently great to cause aluminum to deposited at a greater rate on the portion of the metal-containing layer within the recess.

Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.