Abstract: According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal.

Abstract: A current driving type transmitter using independent current signals, which can independently generate and transmit differential current indicating a logic state of data to be transmitted, using a difference between positive data current and negative data current without using external current, so that magnitudes of current applied to a pair of transmission lines can be kept constant without being influenced by the design of current sources and processing factors, a current driving type receiver using independent current signals, which can simultaneously convert a difference in levels of current, received through the transmission lines, into a voltage level by a single I-V converter, so that errors of a true line and a bar line can be lessened, and an interface system for COG application, which adopts the transmitter and receiver, so that distortion of transmitted signals can be reduced.

Abstract: A context-aware role-based access control system and a control method thereof. The context-aware role-based access control system includes: a context-aware user assignment manager (CAUAM) for performing a role assignment function, a role delegation function, or a role revocation function for a user according to a context of the user, based on a preset context request condition; a context-aware permission assignment manager (CAPAM) for performing a permission modification, a permission restoration, and a personalized permission modification for a permission, which the role has, according to changes in the context of the user; an information repository for storing a user profile and context information; and an access control manager (ACM) for controlling the context-aware user assignment manager, the context-aware permission assignment manager, and the information repository, and processing an access control request.

Abstract: A laser projection display and a method of compensating for image distortion of the same stereoscopic liquid crystal display device having a touch panel and a method for manufacturing the same are disclosed. Herein, the method includes displaying a picture including a red image, a green image, and a blue image, selecting one of the red image, the green image, and the blue image so as to perform pixel alignment of the picture, calculating pixel coordinate values x+dx and y+dy corresponding to the selected image (herein, x represents the x coordinate value prior to alignment, y represents the y coordinate value prior to alignment, dx represents a varied x coordinate value after alignment, and dy represents a varied y coordinate value after alignment), calculating distortion compensation coordinate values X? and Y? corresponding to the pixel coordinate values x+dx and y+dy, and mapping the distortion compensation values X? and Y?, thereby compensating for an image distortion occurring in the selected image.

Abstract: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

Abstract: A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.

Abstract: Differential current driving type transmitter and receiver, and an interface system having the transmitter and receiver. The transmitter includes a current source, a current direction selecting block, and a balancing switch block. The current source sources currents to a pair of transmission lines or sinks currents flowing through the pair of transmission lines. The current direction selecting block transfers a current flowing from the current source to one transmission line of the pair of transmission lines and a current flowing through the other transmission line of the pair of transmission lines to the current source. The balancing switch block initializes the pair of transmission lines to a balanced state.

Abstract: Provided is a technology for preventing noisy data from being displayed before valid data is inputted when power is turned on in a liquid crystal display.

Abstract: A server cluster and method for providing a push notification service are provided. The method includes searching for, by a management server cluster, a first push server corresponding to predetermined search criteria from among a plurality of push servers upon receiving a request to connect with a push server from a mobile terminal; providing, by the management server cluster, connection information regarding the found first push server to the mobile terminal; and delivering, by the first push server, upon generation of a notification event after connecting with the mobile terminal, event information corresponding to the push notification event to the connected mobile terminal.

Abstract: Provided is an apparatus and method for transmitting a push notification message. To this end, connection is performed with a mobile terminal, and if a push notification message is received from a push notification service providing server, the received push notification message is transmitted to the mobile terminal, and when disconnected from the mobile terminal, a push notification message received after the disconnection is stored, such that transmission of the push notification message can be guaranteed.

Abstract: Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: An automatic brightness adjusting method and apparatus for image signal processor (ISP) is provided. The image processing apparatus may include a histogram generating unit, a cumulative distribution function calculator, and a histogram equalization (HE) unit. The histogram generating unit may generate a histogram of brightness values of pixels in an input image. The cumulative distribution function calculator may generate a cumulative distribution function and an inverse cumulative distribution function, based on the generated histogram. The HE unit may generate a conversion function based on the cumulative distribution function and the inverse cumulative distribution function, and may apply HE to the input image based on the conversion function so as to generate an output image.

Abstract: Differential current driving type transmitter and receiver, and an interface system having the transmitter and receiver. The transmitter includes a current source, a current direction selecting block, and a balancing switch block. The current source sources currents to a pair of transmission lines or sinks currents flowing through the pair of transmission lines. The current direction selecting block transfers a current flowing from the current source to one transmission line of the pair of transmission lines and a current flowing through the other transmission line of the pair of transmission lines to the current source. The balancing switch block initializes the pair of transmission lines to a balanced state.

Abstract: The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.

Abstract: A chip-on-glass (COG) type liquid crystal display device minimizes a reflected wave from an input terminal of a source driver IC, regardless of the resistance value of a transmission line on a glass substrate, through the use of impedance matching at a front terminal of an LOG and impedance matching at an output terminal of a timing controller, thereby enhancing the frequency characteristic while maintaining a slim and lightweight design, so that it is possible to express a high-resolution high-quality image.

Abstract: A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.

Abstract: A current driving type transmitter using independent current signals, which can independently generate and transmit differential current indicating a logic state of data to be transmitted, using a difference between positive data current and negative data current without using external current, so that magnitudes of current applied to a pair of transmission lines can be kept constant without being influenced by the design of current sources and processing factors, a current driving type receiver using independent current signals, which can simultaneously convert a difference in levels of current, received through the transmission lines, into a voltage level by a single I-V converter, so that errors of a true line and a bar line can be lessened, and an interface system for COG application, which adopts the transmitter and receiver, so that distortion of transmitted signals can be reduced.

Abstract: In the transmitter, receiver and interface system capable of selective adoption of a differential current driving scheme and a differential voltage driving scheme, a differential current driving scheme and a differential voltage driving scheme can be selectively adopted in one semiconductor chip depending upon the states of the transmission lines, so that effective data transmission is possible and common parts can be shared, whereby a design time can be shortened and a layout area can be reduced.

Abstract: The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.

Abstract: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.