Abstract: An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.

Abstract: Example embodiments relate to a semiconductor memory module and memory system, and a method of communicating therein. According to an example embodiment, a semiconductor memory system may include a memory controller, M interconnected memory elements, and/or N data buses, where N is a natural number and M is a divisor of N. The N data buses may connect the M memory elements to the memory controller. Each memory element may use N/M of the N number of data buses.

Abstract: A semiconductor device is provided including a printed circuit board and first, second and third rows of power and/or signal pads on the printed circuit board. A plurality of input and output buffers are also provided. Ones of the plurality of input and output buffers are provided between the first and second rows and others of the plurality of input and output buffers are provided between the second and third rows. Related methods of fabricating semiconductor devices are also provided.

Abstract: In an improved construction of a memory device, the memory device includes a first group of pins via which a command/address signals are received and via which data signals are received, and a second group of pins via which the command/address signals are received and via which data signals are output. When the data signals are input to the first group of pins, the command/address signals are received via the second group of pins. When the data signals are output from the second group of pins, the command/address signals are received via the first group of pins.

Abstract: An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

Abstract: Provided are a simultaneous bi-directional (SBD) buffer including a self-test circuit having a function of generating an input signal. By using the self-test circuit, self-testing can be accurately performed by generating the input signal in a self-test mode, and a self-test method used by the SBD buffer. The SBD buffer includes an output driver, an input receiver, a first multiplexer, and an input signal generating circuit. The output driver receives an output data signal and outputs the received output data signal to an input/output node. The input receiver receives a signal generated by combining an input data signal inputted to the input/output node with the output data signal, compares the voltage level of the signal with a reference voltage, and outputs the comparison result. The first multiplexer outputs the reference voltage in response to a reference voltage selection signal.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

Abstract: A semiconductor memory device that may include output drivers, each of which varies a data swing width in response to a correction code, and one or more data swing width control portions. Each of the data swing width control portions may correspond to an output driver, may vary the correction code according to a data swing width of the corresponding output driver to change the data swing width to a correction swing width, and then varies the correction code again to the extent that data of the corresponding output driver are normally transmitted, which may reduce the data swing width.

Abstract: An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

Abstract: The open-drain type output buffer includes a first driver and at least one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and does not pull the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the first state when it has been determined that at least two consecutive high voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated.

Abstract: A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

Abstract: A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to transfer a plurality of chip select signals provided from an external device to the plurality of memory chips.

Abstract: Provided is a semiconductor device with improved signal transmission characteristics. The semiconductor device includes a substrate and a semiconductor chip. The substrate includes connection pads mounted in a central area of a top surface of the substrate, balls attached to a bottom surface of the substrate, and an area on the bottom of the substrate directly below the connection pads which is depopulated of balls. The semiconductor chip Whose bottom surface is mounted on one of the two sections has an edge-pad structure in which chip pads are disposed on a portion of a top surface so as to be adjacent to the connection pads. The connection pads are connected to the corresponding chip pads by bonding wires. The semiconductor chip is less than half the size of the substrate. The chip pads are disposed in the same direction as the connection pads. The connection pads are aligned in one or more rows in a central area of the substrate.

Abstract: In an improved construction of a memory device, the memory device includes a first group of pins via which a command/address signals are received and via which data signals are received, and a second group of pins via which the command/address signals are received and via which data signals are output. When the data signals are input to the first group of pins, the command/address signals are received via the second group of pins. When the data signals are output from the second group of pins, the command/address signals are received via the first group of pins.

Abstract: Test board configurations and test method for semiconductor devices with simultaneous bi-directional (SBD) data ports are disclosed. The devices have two SBD data ports with a pass mode that relays data between the ports. Significantly, each device contains configurable switching elements that allow a test mode, wherein unidirectional input/output data on one SBD data port is mapped to bi-directional data on the other SBD data port. This allows device testing with automated test equipment that employs unidirectional data signaling, and yet allows such test equipment to test the SBD capability of such devices.

Abstract: A data transmission circuit includes a control signal generation circuit, a write state machine, a conversion circuit, a read state machine, and a selection circuit. The control signal generation circuit receives a strobe signal and a clock signal in response to an enable signal, generates a write control signal that is activated in response to a rising edge of the strobe signal, and generates a read control signal that is activated in response to a first rising or falling edge of the clock signal after the write control signal is activated. The write state machine is activated in response to the write control signal, changes its internal state in synchronization with the strobe signal, and sequentially outputs input control signals in response to the changed internal state. The conversion circuit converts serial data to parallel data in response to the input control signal sequentially output from the write state machine and latches the parallel data.

Abstract: Disclosed is a data detector for detecting data placed on a bi-directional data channel having two nodes. The data on the data channel is a combination of data placed on the data channel at both nodes. The data detector at the first node compares data received from the data channel to multiple reference voltages. Which reference voltages are used for comparison is determined by the state of data placed on the data channel at the first node. By comparing the data from the data channel to more than one reference voltage data can be detected with a swing margin of about 50%, such that it is less affected by noise, power or other glitches than are conventional circuits. Methods of detecting data are also disclosed.