Abstract: In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions.

Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.

Abstract: A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.

Abstract: Example embodiments disclose a semiconductor device having an on-die termination (ODT) structure that reduces current consumption, and a termination method performed in the semiconductor device. The semiconductor device includes a calibration circuit for generating calibration codes in response to a reference voltage and a voltage of a calibration terminal connected to an external resistor and an on-die termination device for controlling a termination resistance of a data input/output pad in response to the calibration codes and an on-die termination control signal. The termination resistance of the data input/output pad is greater than a resistance of the calibration terminal.

Abstract: A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval.

Abstract: A laser projection display and a method of compensating for image distortion of the same stereoscopic liquid crystal display device having a touch panel and a method for manufacturing the same are disclosed. Herein, the method includes displaying a picture including a red image, a green image, and a blue image, selecting one of the red image, the green image, and the blue image so as to perform pixel alignment of the picture, calculating pixel coordinate values x+dx and y+dy corresponding to the selected image (herein, x represents the x coordinate value prior to alignment, y represents the y coordinate value prior to alignment, dx represents a varied x coordinate value after alignment, and dy represents a varied y coordinate value after alignment), calculating distortion compensation coordinate values X? and Y? corresponding to the pixel coordinate values x+dx and y+dy, and mapping the distortion compensation values X? and Y?, thereby compensating for an image distortion occurring in the selected image.

Abstract: Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.

Abstract: A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.

Abstract: A semiconductor memory device that may include output drivers, each of which varies a data swing width in response to a correction code, and one or more data swing width control portions. Each of the data swing width control portions may correspond to an output driver, may vary the correction code according to a data swing width of the corresponding output driver to change the data swing width to a correction swing width, and then varies the correction code again to the extent that data of the corresponding output driver are normally transmitted, which may reduce the data swing width.

Abstract: A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to transfer a plurality of chip select signals provided from an external device to the plurality of memory chips.

Abstract: A context-aware role-based access control system and a control method thereof. The context-aware role-based access control system includes: a context-aware user assignment manager (CAUAM) for performing a role assignment function, a role delegation function, or a role revocation function for a user according to a context of the user, based on a preset context request condition; a context-aware permission assignment manager (CAPAM) for performing a permission modification, a permission restoration, and a personalized permission modification for a permission, which the role has, according to changes in the context of the user; an information repository for storing a user profile and context information; and an access control manager (ACM) for controlling the context-aware user assignment manager, the context-aware permission assignment manager, and the information repository, and processing an access control request.

Abstract: Driving a light scanner at a resonant frequency of the light scanner using a phase delay compensated driving signal.

Abstract: A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of a plurality of input/output pads; a pipelined circuit unit, which is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with predetermined clock signals through an input/output path selected in response to pipeline enable signals; and a plurality of selection units, which are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals.

Abstract: A menu user interface providing device and a method thereof are disclosed. In accordance with an embodiment of the present invention, the method of providing a menu user interface by a portable apparatus, including determining whether a main menu icon displayed on a touch screen is selected; determining whether a menu mode is an activation mode or an inactivation mode if the main menu icon is selected; and changing the menu mode into the activation mode if the menu mode is determined as the inactivation mode and forming an expanded menu by radically arranging a submenu of n hierarchies, n being a natural number, corresponding to the main menu icon and displaying the formed expanded menu through a touch screen. Accordingly, with the present invention, a user interface capable of inputting various data with easy manipulation and minimized multi-points can be provided.

Abstract: Disclosed is a method and system for controlling access for a mobile agent in a home network environment. The method includes the steps of: issuing a role ticket to the mobile agent; verifying access authority to service requested by the mobile agent through the role ticket; and granting the mobile agent access authority to the service. Accordingly, a table for managing access authority of a user is distributed to devices, so that it is possible to provide the mobile agent access control method and system capable of minimizing network traffic in the home network environment.

Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.

Abstract: The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.