Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Abstract: In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.

Abstract: The present invention relates to a vertical furnace for fabricating an artificially lightweight fine-aggregates in that the aggregates can be fired in the vertical furnace in a floating state, so that the contacting time between the aggregates can be minimized, thereby preventing the adhesion between the aggregates and manufacturing the artificially lightweight fine-aggregates as an insulating concrete for building material, sound-absorbing materials, and lagging material.

Abstract: There are provided a method for manufacturing a barium titanate powder and a barium titanate powder manufactured by the same. The method for manufacturing the barium titanate powder according to an exemplary embodiment of the present invention includes: preparing a titanium dioxide (TiO2) powder having a specific surface area of 90 m2/g or more and a barium carbonate (BaCO3) powder having a specific surface area of 40 m2/g or more; mixing the titanium dioxide powder, the barium carbonate powder, and a dispersant so as to have a specific surface area of a mixed powder of 50 m2/g or more; performing a primary heat treatment of the mixed powder by decompressing the mixed powder at a temperature where a weight decreasing rate of the mixed powder is equal to or more than 90%; and performing a secondary heat treatment of the mixed powder at a temperature of 850° C. or less.

Abstract: Provided are a semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package may include a circuit substrate, a semiconductor chip mounted on the circuit substrate, a chip package interaction disposed between the circuit substrate and the semiconductor chip, a first molding portion covering part of the semiconductor chip and part of the chip package interaction, a second molding portion formed on the first molding portion, and an adhesion portion adhering the first and second molding portions to each other, the adhesion portion being disposed between the first and second molding portions.

Abstract: Some embodiments provide a semiconductor device including a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion that supports the protruding portion. Methods of fabricating the same are also provided.

Abstract: A varistor comprises a main body having first and second external terminals formed on the outer surface thereof, a first withdrawn terminal plate joined to the first external terminal, and a second withdrawn terminal plate joined to the second external terminal, wherein the melting point of a second bonding material for allowing the second withdrawn terminal plate and the second external terminal to be joined to each other is lower than that of a first bonding material for allowing the first withdrawn terminal plate and the first external terminal to be joined to each other.

Abstract: A server, a user terminal and a method of providing service by uploading at least one content list generated by packaging a plurality of content, extracting a core content by considering a packaging frequency for each content included in the at least one content list; and recommending an extracted core content to a user if requested by a user.

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract: Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.

Abstract: Provided is a semiconductor chip including a back side insulation structure. The semiconductor chip may include a semiconductor layer including an active surface and an inactive surface facing each other; the insulating layer includes a first surface adjacent to the inactive surface and a second surface facing the first surface. The insulating layer is disposed on the inactive surface of the semiconductor layer. A penetrating electrode fills a hole penetrating the semiconductor layer and the insulating layer. The through electrode comprises a protrusive portion protruding from the second surface of the insulating layer.

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern.

Abstract: A vision inspection system and a workpiece inspection method are used in inspecting a workpiece. The vision inspection system includes a level block having an upper surface whose opposite end regions are defined as a first position and a second position. A first transfer device has a table for supporting the workpiece. The first transfer device is installed on the upper surface of the level block for rectilinearly moving the table between the first position and the second position. A camera is arranged above the level block for taking an image of the workpiece to output image data. A second transfer device is installed on the upper surface of the level block for rectilinearly moving the camera between the first position and the second position. A computer is connected to the first transfer means, the camera and the second transfer means to control them in a specified manner.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

Abstract: Disclosed herein is a secondary battery pack including a battery cell having a pair of coupling grooves, each of the coupling grooves having a predetermined depth, an insulative mounting member mounted to the top of the battery cell, a protection circuit module (PCM) having a pair of connection coupling members protruding downward, and an insulative cap coupled to the top of the battery cell, wherein the connection coupling members are inserted into coupling grooves formed at electrode terminals of the battery cell through openings of the insulative mounting member in a state in which the insulative mounting member is mounted to the top of the battery cell, thereby achieving the coupling of the PCM to the battery cell and the insulative mounting member and the electrical connection between the battery cell and the PCM.

Abstract: Disclosed herein is a secondary battery pack including a battery cell having an electrode assembly of a cathode/separator/anode structure mounted in a battery case together with an electrolyte in a sealed state, an insulative mounting member having openings, through which electrode terminals of the battery cell are exposed to the outside, the insulative mounting member being configured to have a structure in which a safety element is mounted to the top of the insulative mounting member, the insulative mounting member being disposed in direct contact with the top of the battery cell, and an insulative cap coupled to the top of the battery cell so that the insulative cap surrounds the insulative mounting member in a state in which the safety element is mounted to the insulative mounting member, wherein the battery case is provided at the top thereof with a coupling groove, and the insulative cap is provided at the bottom thereof with a coupling protrusion formed in a shape corresponding to the coupling groove,