Abstract: Microelectronic devices include a conductive via that extends into a substrate face and that also protrudes beyond the substrate face to define a conductive via end surface and a conductive via sidewall that extends from the end surface towards the substrate face. A conductive cap is provided on the end surface, the conductive cap including a conductive cap body that extends across the end surface and a flange that extends from the conductive cap body along the conductive via sidewall towards the substrate face. Related fabrication methods are also described.

Abstract: A mobile terminal and a method of controlling the mobile terminal are provided. The mobile terminal may generate a haptic effect whose intensity or pattern corresponds to the type and importance of an event occurred therein. Therefore, it is possible for a user to easily identify the event based on the haptic effect. Since the mobile terminal generates a haptic effect in response to a command input thereto by the user, it is possible to prevent a command from being accidently input to the mobile terminal.

Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

Abstract: One or more embodiments of the present invention describe a novel use of capsanthin and/or fatty-acyl ester of capsanthin to inhibit both the differentiation of pre-adipocytes to adipocytes and the accumulation of fat in the adipocytes. One or more embodiments of the present invention are based on findings that capsanthin contained in some natural products such as red pepper, paprika, bell pepper, etc. have anti-adipogenic activity by inhibiting both the differentiation of pre-adipocyte into adipocyte and the accumulation of fat in adipocytes, Therefore, this findings provide a functional food and a pharmaceutical composition wherein capsanthins and the extract of any natural products containing the same components are included in the functional food and the pharmaceutical composition, to offer obesity prevention and/or treatment effects.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract: The present invention relates to a method of regulating mammalian target-of-rapamycin (mTOR) by regulating a phospholipase D (PLD) activity that generates a complex with mTOR. Further, the present invention also relates to a method of screening inhibitors of mTOR, and a method and a composition for treating mTOR-related metabolic diseases by inhibiting mTOR.

Abstract: There are provided a method of manufacturing a ceramic powder having a perovskite structure and a ceramic powder having a perovskite structure manufactured by the same. The method includes: mixing a compound of an element corresponding to site A in an ABO3 perovskite structure as well as a compound of an element corresponding to site B in the same structure, with supercritical water in a continuous mode to form seed crystals; and mixing the seed crystals in a batch mode to conduct grain growth thereof.

Abstract: A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: The present invention relates to a novel iridium complex into which carbazole-substituted pyridine derivatives and various substituents-substituted phenyl derivatives are introduced as main ligand and a electrophosphorescence diode containing the same as a dopant of a light-emitting layer. When the iridium complex according to the present invention is applied to an organic light-emitting diode, the heat-resistance property and the light-emitting property can be significantly improved as well as the light-emitting efficiency and the like can be significantly improved by doping the iridium complex compound into the light-emitting layer as compared to the conventional organic light-emitting diode.

Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Abstract: In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.

Abstract: The present invention relates to a vertical furnace for fabricating an artificially lightweight fine-aggregates in that the aggregates can be fired in the vertical furnace in a floating state, so that the contacting time between the aggregates can be minimized, thereby preventing the adhesion between the aggregates and manufacturing the artificially lightweight fine-aggregates as an insulating concrete for building material, sound-absorbing materials, and lagging material.

Abstract: There are provided a method for manufacturing a barium titanate powder and a barium titanate powder manufactured by the same. The method for manufacturing the barium titanate powder according to an exemplary embodiment of the present invention includes: preparing a titanium dioxide (TiO2) powder having a specific surface area of 90 m2/g or more and a barium carbonate (BaCO3) powder having a specific surface area of 40 m2/g or more; mixing the titanium dioxide powder, the barium carbonate powder, and a dispersant so as to have a specific surface area of a mixed powder of 50 m2/g or more; performing a primary heat treatment of the mixed powder by decompressing the mixed powder at a temperature where a weight decreasing rate of the mixed powder is equal to or more than 90%; and performing a secondary heat treatment of the mixed powder at a temperature of 850° C. or less.

Abstract: Provided are a semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package may include a circuit substrate, a semiconductor chip mounted on the circuit substrate, a chip package interaction disposed between the circuit substrate and the semiconductor chip, a first molding portion covering part of the semiconductor chip and part of the chip package interaction, a second molding portion formed on the first molding portion, and an adhesion portion adhering the first and second molding portions to each other, the adhesion portion being disposed between the first and second molding portions.