Patents by Inventor Jung Hyuk Yoon

Jung Hyuk Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998043
    Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, In Soo Lee
  • Publication number: 20210117321
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Publication number: 20210104277
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Ki Won LEE, Jung Hyuk YOON
  • Publication number: 20210020242
    Abstract: A nonvolatile memory apparatus may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When the selected memory cell was snapped back, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to write data. When the selected memory cell is not snapped back, the write circuit may apply no voltage and no current to the selected memory cell. The sense amplifier may sense whether the selected memory cell was snapped back.
    Type: Application
    Filed: February 27, 2020
    Publication date: January 21, 2021
    Applicant: SK hynix Inc.
    Inventor: Jung Hyuk YOON
  • Patent number: 10878903
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Jung Hyuk Yoon
  • Publication number: 20200402575
    Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.
    Type: Application
    Filed: January 28, 2020
    Publication date: December 24, 2020
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, In Soo LEE
  • Patent number: 10748610
    Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung Hyuk Yoon
  • Patent number: 10546635
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 10437749
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a write circuit, a first selection circuit, a memory cell, a coupling control circuit, and a coupling circuit. The write circuit may generate a write current corresponding to write data based on a control code signal. The first selection circuit may couple the write circuit to a first line based on a first selection signal, and may allow cell current corresponding to the write current to flow to the first line. The memory cell may be coupled between the first line and a second line, and may store the write data based on the cell current. The coupling control circuit may generate a coupling code signal corresponding to the write current based on the control code signal. The coupling circuit may selectively couple one or more voltage terminals among a plurality of voltage terminals to the second line based on a coupling code signal.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyuk Yoon, Ho-Seok Em
  • Patent number: 10395735
    Abstract: An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. The semiconductor memory may include a first selection circuit configured for coupling the first write circuit to a first line based on a first selection signal. The semiconductor memory may include a second write circuit configured for generating a second current. The semiconductor memory may include a second selection circuit configured for coupling the second write circuit to a second line based on a second selection signal. The semiconductor memory may include a memory cell coupled between the first line and the second line. The semiconductor memory may include a voltage control circuit configured for controlling a voltage level of the second line.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventor: Jung-Hyuk Yoon
  • Publication number: 20190214084
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Application
    Filed: September 24, 2018
    Publication date: July 11, 2019
    Applicant: SK hynix Inc.
    Inventors: Ki Won LEE, Jung Hyuk YOON
  • Publication number: 20190198102
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN
  • Publication number: 20190198101
    Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: SK hynix Inc.
    Inventor: Jung Hyuk YOON
  • Patent number: 10297313
    Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: Jung Hyuk Yoon
  • Patent number: 10249367
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 10210927
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Publication number: 20180358085
    Abstract: A semiconductor memory apparatus may include a memory cell, a write driver, and a voltage adjustment circuit. The write driver may provide the memory cell with a program current based on a write data. The voltage adjustment circuit may adjust a voltage level of a global word line coupled to the memory cell when a current flowing through the memory cell or the voltage level of the global word line is greater than a threshold value.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: SK hynix Inc.
    Inventors: Ho Seok EM, Jung Hyuk YOON
  • Publication number: 20180144798
    Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 24, 2018
    Applicant: SK hynix Inc.
    Inventor: Jung Hyuk YOON
  • Publication number: 20170236583
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN
  • Publication number: 20170236582
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN