Abstract: Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled.

Abstract: Disclosed is a semiconductor memory device. A semiconductor memory device in accordance with an embodiment of the present invention includes a write driver configured to provide voltage necessary for a write operation when the write operation is performed, a switch block connected to the write driver and configured to control the path of the write voltage, and a cell block connected to the switch block, wherein a constant voltage is supplied to a node leading to a cell selection path within the cell block using the write driver as a voltage source.

Abstract: A non-volatile memory device for measuring a read current of a unit cell is provided. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection signal, a sense amplifier controlled by a sense-amplifier enable signal, configured to sense and amplify data that is received from the unit cell through the column switching unit, a first latch unit configured to latch the sense-amplifier enable signal for a predetermined time when a test code signal received from an external part is activated, a column controller configured to output a latch control signal in response to a combination of a column switch-off signal and a column control signal, and a second latch unit configured to control whether or not the column selection signal is latched in response to an activation state of the latch control signal.

Abstract: A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal.

Abstract: A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal.

Abstract: A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node.

Abstract: A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

Abstract: A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal.

Abstract: A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

Abstract: A non-volatile memory device for measuring a read current of a unit cell is disclosed. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection signal, a sense amplifier controlled by a sense-amplifier enable signal, configured to sense and amplify data that is received from the unit cell through the column switching unit, a first latch unit configured to latch the sense-amplifier enable signal for a predetermined time when a test code signal received from an external part is activated, a column controller configured to output a latch control signal in response to a combination of a column switch-off signal and a column control signal, and a second latch unit configured to control whether or not the column selection signal is latched in response to an activation state of the latch control signal.

Abstract: A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node.