Patents by Inventor Jung-Hyun Kwon

Jung-Hyun Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438655
    Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon, Yong Ju Kim, Do Sun Hong
  • Publication number: 20190303253
    Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.
    Type: Application
    Filed: December 6, 2018
    Publication date: October 3, 2019
    Applicant: SK hynix Inc.
    Inventors: Wongyu SHIN, Jung Hyun KWON, Seunggyu JEONG, Do Sun HONG
  • Publication number: 20190287587
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Application
    Filed: November 19, 2018
    Publication date: September 19, 2019
    Inventors: Dong Hyun KIM, Dae Han KWON, Kwan Su SHON, Soon Ku KANG, Jung Hyun SHIN, Doo Bock LEE, Yo Han JEONG, Eun Ji CHOI, Tae Jin HWANG
  • Publication number: 20190286372
    Abstract: The present invention relates to memory apparatuses and an operating methods using a heterogeneous memory array. An operation method of a memory apparatus using a heterogeneous memory array according to an embodiment of the present invention includes dividing an input bit into at least one data bit according to a mode bit, and writing the divided data bits in each cell of the memory array by using a cell level of the memory array which is configured according to the mode bit.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Applicant: Research & Business Foundation Sungkyunkwan University
    Inventors: Joon Sung YANG, Tae Hyun KWON, Imran MUHAMMAD, Jung Min YOU
  • Publication number: 20190278706
    Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.
    Type: Application
    Filed: October 24, 2018
    Publication date: September 12, 2019
    Inventors: Do-Sun HONG, Jung Hyun KWON, Won Gyu SHIN, Seung Gyu JEONG
  • Publication number: 20190273247
    Abstract: Composite particles and a negative electrode active material including such particles for an electrochemical device. The negative electrode active material is capable of lithium intercalation/deintercalation and includes composite particles including a carbon phase including a carbonaceous material, silicon (Si) and lithium fluoride (LiF). The Si and LiF may be present as Si—LiF mixed particles, which are dispersed in the carbon phase, wherein the Si—LiF mixed particles are dispersed in the carbon phase with uniform or non-uniform distribution. In addition, the composite particles include the carbon phase mixed uniformly or amorphously with the Si—LiF mixed particles.
    Type: Application
    Filed: December 22, 2017
    Publication date: September 5, 2019
    Applicant: LG CHEM, LTD.
    Inventors: So-Ra LEE, Seo-Young KWON, Jee-Eun KIM, Ji-Young PARK, Pil-Kyu PARK, Hyeon-Min SONG, Kwi-Sub YUN, U-Jin YOON, Jae-Young LEE, Yong-Ju LEE, Jung-Hyun CHOI
  • Publication number: 20190267055
    Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
    Type: Application
    Filed: December 5, 2018
    Publication date: August 29, 2019
    Applicant: SK hynix Inc.
    Inventors: Seunggyu JEONG, Jung Hyun KWON, Wongyu SHIN, Do Sun HONG
  • Publication number: 20190260097
    Abstract: A wireless battery management system and a battery pack including the same. The wireless battery management system includes a plurality of slave BMSs coupled to a plurality of battery modules installed one-to-one correspondence, and a master BMS configured to wirelessly transmit a trigger signal to the plurality of slave BMSs, the trigger signal being for ID allocation to the plurality of slave BMSs. Each slave BMS is configured to generate a response signal including a temporary ID in response to the trigger signal, each slave BMS having a different temporary ID, and wirelessly transmit the response signal to the master BMS. The master BMS is configured to receive the response signal from each of the plurality of slave BMSs, and determine formal IDs to be allocated to each slave BMS based on a received signal strength of the response signal from the given slave BMS.
    Type: Application
    Filed: June 14, 2018
    Publication date: August 22, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Jung-Hyun Kwon, Chan-Ha Park, Sang-Hoon Lee, Yean-Sik Choi
  • Patent number: 10370002
    Abstract: An engine control method for preventing an engine of a vehicle from stalling on a sloped road includes steps of: detecting whether a shifting lever is in a neutral stage (N-stage); measuring a vehicle speed and a slope angle of the sloped road, and calculating a load acting on a vehicle body on the sloped road; accelerating an engine a first time to increase an engine RPM so that an engine torque is larger than the load; and accelerating the engine a second time to move the vehicle when the shifting lever enters into a driving gear stage (D-stage).
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: August 6, 2019
    Assignee: HYUNDAI MOTOR COMPANY
    Inventors: Tae-Kwang Eom, Jung-Suk Han, Chang-Hyun Lim, Hyeok-Jun Kwon
  • Publication number: 20190237150
    Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.
    Type: Application
    Filed: September 7, 2018
    Publication date: August 1, 2019
    Inventors: Seung-Gyu JEONG, Jung-Hyun KWON, Do-Sun HONG, Won-Gyu SHIN
  • Patent number: 10363794
    Abstract: An air-conditioning control method for calculating an optimum operation amount of an air-conditioning blower in an air-conditioning system of a vehicle includes: determining a heater heat quantity after an engine of the vehicle is started under a maximum heating condition of the air-conditioning system and the air-conditioning system is turned on according to current vehicle state information and air-conditioning information; determining a lost heat quantity discharged outside the vehicle during a current air-conditioning mode; determining an effective heating energy efficiency by calculating a difference between the heater heat quantity and the lost heat quantity; calculating the optimum operation amount of the air-conditioning blower where the effective heating energy is maximized; and controlling operation of the air-conditioning blower according to the determined optimum operation amount.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: July 30, 2019
    Assignee: Hyundai Motor Company
    Inventors: Tae Woong Lim, Jae Hyun Park, Chun Kyu Kwon, Jung Ho Kwon
  • Patent number: 10359950
    Abstract: A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Sang-Gu Jo, Sung-Eun Lee
  • Publication number: 20190220952
    Abstract: Provided is a method of acquiring an optimized closed curved surface image using multiple cameras, and more particularly, an image providing method that produces a single image using a plurality of cameras fixed to a rig and having different capturing viewpoints, the method including projection operation of acquiring a single image by projecting images acquired from the plurality of cameras on a projection surface of a closed curved surface based on parameter information, rendering operation of fitting the acquired single image in a quadrangular frame for each region through a non-uniform sampling process, and viewing operation of mapping the sampled image to a viewing sphere.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 18, 2019
    Inventors: Jung Jin Lee, Seung Hoon Cha, Dae Hyeon Wi, Jae Hwan Kwon, Young Hui Kim, Seung Hwa Jeong, Kye Hyun Kim, Bum Ki Kim
  • Publication number: 20190219752
    Abstract: A color conversion panel includes a substrate, a plurality of color conversion layers and a transmission layer on the substrate, a capping layer on the plurality of color conversion layers and the transmission layer, and a filter layer on the capping layer.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: Seon-Tae Yoon, Hae Il Park, Jung Hyun Kwon, Kwang Keun Lee, Jun Han Lee
  • Patent number: 10353770
    Abstract: An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung-Eun Lee, Jung-Hyun Kwon, Sang-Gu Jo
  • Patent number: 10353048
    Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Embodiments of the present invention provide a device and a method for estimating a position between wireless apparatuses using a signal transmitted and received between wireless apparatuses in a wireless communication system. A device of a first wireless apparatus for estimating a position comprises: a transceiver for transmitting and receiving a signal to and from a second wireless apparatus; and a position estimator for estimating a position of the second wireless apparatus using a signal transmitted and received through the transceiver.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Ho Oh, Jung-Min Yoon, Sang-Hyun Chang, Sung-Rok Yoon, Ohyun Jo, Chang-Yeul Kwon, Kil-Sik Ha
  • Patent number: 10347971
    Abstract: An electronic device is provided. The electronic device includes a first antenna, a first feeding line electrically connected to the first antenna, a second antenna, a second feeding line electrically connected to the second antenna element, a conductive line connecting a point of the first antenna or the first feeding line and a point of the second antenna or the second feeding line, and a sensor module electrically connected to a point of at least one of the first antenna element, the second antenna element, the first feeding line, the second feeding line, and the conductive line.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Young Kwon, Seung Hyun Yeo, Jung Min Lee, Hyun Su Lee, Soon Sang Park, Hyun Suk Choi
  • Patent number: 10330974
    Abstract: An exemplary embodiment of the present disclosure provides a color conversion panel including: a substrate; a polarization layer that is disposed on the substrate and includes a plurality of polarization patterns spaced apart from each other at a predetermined interval; and a color conversion layer that is disposed on the polarization layer, wherein at least one of the plurality of polarization patterns may include an external light interference layer disposed on the substrate and a reflection layer disposed on the external light interference layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang Keun Lee, Jung Hyun Kwon, Young Min Kim, Hae Ii Park, Moon Jung Baek
  • Publication number: 20190188162
    Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.
    Type: Application
    Filed: November 28, 2018
    Publication date: June 20, 2019
    Inventors: Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin, Seung-Gyu Jeong
  • Publication number: 20190189204
    Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.
    Type: Application
    Filed: September 7, 2018
    Publication date: June 20, 2019
    Inventors: Seung-Gyu JEONG, Won-Gyu SHIN, Jung-Hyun KWON, Do-Sun HONG