Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.

Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

Abstract: Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

Abstract: A display device including: a first substrate; a transflective layer disposed on a surface of the first substrate; a wavelength conversion layer disposed on the transflective layer; a capping layer disposed on the wavelength conversion layer; a first polarizing layer disposed on the capping layer; and a second polarizing layer disposed on the other surface of the first substrate. The first polarizing layer and the second polarizing layer have different polarization directions.

Abstract: A buffer system may include a buffer configured to receive input data having an assigned priority level, store the input data within a memory stack regardless of the priority level assigned to the input data, and sequentially output the input data stored in the memory stack in order of the priority levels assigned to the input data.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.

Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.

Abstract: A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

Abstract: A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.

Abstract: A display device and method of manufacturing the same, in which the display device includes: a first substrate; a transflective layer disposed on a surface of the first substrate; a wavelength conversion layer disposed on the transflective layer; a capping layer disposed on the wavelength conversion layer; a first polarizing layer disposed on the capping layer; and a second polarizing layer disposed on the other surface of the first substrate. The first polarizing layer and the second polarizing layer have different polarization directions.

Abstract: A scheduler of a memory system is provided. The scheduler may include a pattern storage part and a pattern selector. The pattern storage part may have a plurality of storage patterns, each of the storage patterns provide for a process sequence for a plurality of instructions. The pattern selector may be configured to select one of the plurality of storage patterns in the pattern storage part and generate a schedule such that external instructions are executed in the process sequence set by the selected storage pattern.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

Abstract: A display device including: a first substrate; a second substrate facing the first substrate; a light-amount adjusting layer interposed between the first substrate and the second substrate; and a backlight unit disposed under the first substrate, wherein the second substrate includes a plurality of color conversion layers respectively disposed on a plurality of pixel regions, the color conversion layer includes a partition wall; and a phosphor disposed on areas defined by the partition wall, and the color conversion layer includes an air layer between the second substrate and the phosphor.

Abstract: A memory system includes a host controller and a cache system. The host controller includes a host queue in which host data including a command outputted from a host are stored. The cache system includes a cache memory having a plurality of sets and a cache controller controlling an operation of the cache memory. The cache controller transmits status information on a certain set to which the host data are to be transmitted among the plurality of sets to the host controller. The host controller receives the status information from the cache controller to determine transmission or non-transmission of the host data stored in the host queue to the cache system.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.