Abstract: A memory system includes a host controller and a cache system. The host controller includes a host queue in which host data including a command outputted from a host are stored. The cache system includes a cache memory having a plurality of sets and a cache controller controlling an operation of the cache memory. The cache controller transmits status information on a certain set to which the host data are to be transmitted among the plurality of sets to the host controller. The host controller receives the status information from the cache controller to determine transmission or non-transmission of the host data stored in the host queue to the cache system.

Abstract: A display device including: a first substrate; a second substrate facing the first substrate; a light-amount adjusting layer interposed between the first substrate and the second substrate; and a backlight unit disposed under the first substrate, wherein the second substrate includes a plurality of color conversion layers respectively disposed on a plurality of pixel regions, the color conversion layer includes a partition wall; and a phosphor disposed on areas defined by the partition wall, and the color conversion layer includes an air layer between the second substrate and the phosphor.

Abstract: A color conversation panel according to an embodiment may include partitioning walls disposed on a substrate, reflective layers disposed on outer surfaces of the partitioning walls, overcoats disposed outside on outer surfaces of the reflective layers and having water repellency, a spacer overlapping a part of the partitioning walls and protruding from a part of the overcoats, the spacer and the overcoats being formed on a same layer, and color conversion layers disposed on the overcoats and disposed in areas defined by the partitioning walls.

Abstract: An error correction method may include performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer may be performed in a second operation mode.

Abstract: A display device includes: a substrate having a display area configured to display an image; a pixel on a first surface of the substrate in the display area and including a display element layer and a pixel circuit layer; a first driver on a second surface of the substrate facing the first surface of the substrate in the display area; and a first connection portion passing through the substrate between the first surface and the second surface of the substrate in the display area to electrically connect a first signal line of the pixel circuit layer and the first driver to each other. The display element layer includes: a first electrode and a second electrode on the same layer and spaced from each other; and a light emitting element between the first electrode and the second electrode.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: A color conversion panel includes a substrate, a plurality of color conversion layers and a transmission layer on the substrate, a capping layer on the plurality of color conversion layers and the transmission layer, and a filter layer on the capping layer.

Abstract: A display device according to the present disclosure includes: a color conversion panel; and a display panel overlapping the color conversion panel, wherein the color conversion panel includes a color conversion layer including a nano-crystalline semiconductor and a transmission layer, the display panel includes a first display panel including a first substrate and a thin film transistor disposed on the first substrate, a second display panel including a second substrate and overlapping the first display panel. The first substrate and the second substrate have different thicknesses.

Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

Abstract: Disclosed herein are a wireless battery management system (BMS) and a battery pack including the same. The wireless BMS includes a plurality of slave BMSs installed and coupled to a plurality of battery modules of the battery pack in one-to-one correspondence, and a master BMS configured to wirelessly transmit a trigger signal to the plurality of slave BMSs for identification (ID) allocation to each of the plurality of slave BMSs. Each slave BMS is configured to generate a response signal including a respective allocated temporary ID in response to the trigger signal, and wirelessly transmit the response signal to the master BMS. For each given slave BMS, the master BMS is configured to receive the response signal from of the given slave BMS, and determine a formal ID to be allocated to the given BMS based on a received signal strength of the response signal.

Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

Abstract: A color conversion panel includes a first color conversion layer, a second color conversion layer, and a light wavelength conversion layer. The first color conversion layer includes a first semiconductor nanocrystal set for providing red light. The second color conversion layer neighbors the first color conversion layer and includes a second semiconductor nanocrystal set for providing first green light. The light wavelength conversion layer neighbors the second light conversion layer, may provide blue light, and includes a third semiconductor nanocrystal set for providing second green light.

Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.

Abstract: A display device according to the present disclosure includes: a color conversion panel; and a display panel overlapping the color conversion panel, wherein the color conversion panel includes a color conversion layer including a nano-crystalline semiconductor and a transmission layer, the display panel includes a first display panel including a first substrate and a thin film transistor disposed on the first substrate, a second display panel including a second substrate and overlapping the first display panel. The first substrate and the second substrate have different thicknesses.

Abstract: A color conversion panel includes a first color conversion layer, a second color conversion layer, and a light wavelength conversion layer. The first color conversion layer includes a first semiconductor nanocrystal set for providing red light. The second color conversion layer neighbors the first color conversion layer and includes a second semiconductor nanocrystal set for providing first green light. The light wavelength conversion layer neighbors the second light conversion layer, may provide blue light, and includes a third semiconductor nanocrystal set for providing second green light.

Abstract: A display device includes a first substrate, a second substrate, a first auxiliary substrate, a second auxiliary substrate, and a display layer. The second substrate includes a display area and a non-display area. The display area overlaps the first substrate. The non-display area extends beyond the first substrate. The first auxiliary substrate includes a first section and a second section. The first section is between the first substrate and the display area. The second section overlaps the non-display area and is bent relative to the first section. The second auxiliary substrate includes a first part and a second part. The first part is between the first section and the display area. The second part overlaps the non-display area and is bent relative to the first part. The display layer is between the first section and the first part and includes pixels that overlap the display area.

Abstract: A backlight unit including: a base substrate in which a light emitting area and a non-light emitting area are defined; a wiring layer including: a lower conductive layer disposed on the base substrate; an intermediate conductive layer disposed on the lower conductive layer; and an upper conductive layer disposed on the intermediate conductive layer; a light emitting element disposed on the wiring layer in the light emitting area; a connection member electrically connecting the light emitting element and the wiring layer, the connection member contacting the intermediate conductive layer of the wiring layer and the light emitting element; a backlight flexible substrate electrically connected to the wiring layer in the non-light emitting area; and a pad connection member electrically connecting the wiring layer and the backlight flexible substrate in the non-light emitting area, the pad connection member contacting the upper conductive layer of the wiring layer.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.