Patents by Inventor Jung Ko
Jung Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970547Abstract: The present disclosure relates to a novel anti-HER2 antibody or an antigen-binding fragment thereof used in the prevention or treatment of cancer, a chimeric antigen receptor including the same, and uses thereof. The antibody of the present disclosure is an antibody that specifically binds to HER2 which is highly expressed in cancer cells (particularly, breast cancer or gastric cancer cells), and binds to an epitope that is different from an epitope to which trastuzumab binds.Type: GrantFiled: April 10, 2023Date of Patent: April 30, 2024Assignee: GC Cell CorporationInventors: Jong Seo Lee, Kyu Tae Kim, Young Ha Lee, In Sik Hwang, Bong Kook Ko, Eunji Choi, You-Sun Kim, Jeongmin Kim, Miyoung Jung, Hoyong Lim, Sungyoo Cho
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Publication number: 20240137511Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION KOREA AEROSPACE UNIVERSITY, HANBAT NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Jin-Ho LEE, Jung-Won KANG, Hyunsuk KO, Sung-Chang LIM, Dong-San JUN, Ha-Hyun LEE, Seung-Hyun CHO, Hui-Yong KIM, Hae-Chul CHOI, Dae-Hyeok GWON, Jae-Gon KIM, A-Ram BACK
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Publication number: 20240129749Abstract: Provided is a reflector/scatterer arranged around a side lobe beam which is generated from a transmission antenna, in a radiation direction of the side lobe beam, for use in expanding a communication service coverage area.Type: ApplicationFiled: June 13, 2023Publication date: April 18, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jung Ick MOON, Myung Sun SONG, In Kui CHO, Gwangzeen KO, Sang-Won KIM, Seong-Min KIM
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Publication number: 20240115706Abstract: The present disclosure pertains to a GUCY2C-binding polypeptide and uses thereof and, specifically, to a GUCY2C-binding polypeptide, a fusion protein including same, a chimeric antigen receptor, an immune cell expressing the chimeric antigen receptor, and a use thereof for treatment and/or diagnosis of cancer.Type: ApplicationFiled: April 7, 2022Publication date: April 11, 2024Applicant: LG CHEM, LTD.Inventors: Youngkyun KIM, Jung Youn SHIN, Yeongrim KO, Soyeon YANG, Beom Ju HONG, Eunhye CHOI, Nakyoung LEE
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Patent number: 11943447Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus that perform inter-prediction using a motion vector predictor. For a candidate block in a col picture, a scaled motion vector is generated based on a motion vector of the candidate block. When the scaled motion vector indicates a target block, a motion vector predictor of the target block is generated based on the motion vector of the candidate block. The motion vector predictor is used to derive the motion vector of the target block in a specific inter-prediction mode such as a merge mode and an AMVP mode.Type: GrantFiled: July 13, 2022Date of Patent: March 26, 2024Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION KOREA AEROSPACE UNIVERSITYInventors: Sung-Chang Lim, Jung-Won Kang, Hyunsuk Ko, Jin-Ho Lee, Ha-Hyun Lee, Dong-San Jun, Hui-Yong Kim, Yung-Lyul Lee, Nam-Uk Kim, Jae-Gon Kim
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Patent number: 11939505Abstract: Provided are a silicon nitride film etching composition, a method of etching a silicon nitride film using the same, and a manufacturing method of a semiconductor device. Specifically, a silicon nitride film may be stably etched with a high selection ratio relative to a silicon oxide film, and when the composition is applied to an etching process at a high temperature and a semiconductor manufacturing process, not only no precipitate occurs but also anomalous growth in which the thickness of the silicon oxide film is rather increased does not occur, thereby minimizing defects and reliability reduction.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: ENF Technology Co., Ltd.Inventors: Dong Hyun Kim, Hyeon Woo Park, Sung Jun Hong, Myung Ho Lee, Myung Geun Song, Hoon Sik Kim, Jae Jung Ko, Myong Euy Lee, Jun Hyeok Hwang
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Publication number: 20240094787Abstract: A manufacturing method of a tiling electronic device includes the following steps. A first electronic panel is provided. The first electronic panel includes multiple first bumps and multiple first conducting lines, and the first bumps and the first conducting lines are disposed on a side surface of the first electronic panel. A second electronic panel is provided. The second electronic panel includes multiple second bumps and multiple second conducting lines, and the second bumps and the second conducting lines are disposed on a side surface of the second electronic panel. The first electronic panel and the second electronic panel are coupled through the first bumps and the second bumps. Multiple conducting elements are formed, so that the first conducting lines are electrically connected with the second conducting lines through the conducting elements after the first electronic panel and the second electronic panel are coupled.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: Innolux CorporationInventors: Wan-Ling Huang, Jian-Jung Shih, Jui-Feng Ko, Tsau-Hua Hsieh
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Publication number: 20240097291Abstract: The present invention relates to a cylindrical lithium ion secondary battery which, when an upper end of a cylindrical can is clamped, can prevent deformation of a cap assembly so as to improve safety. For an example, a cylindrical lithium ion secondary battery is disclosed, the battery comprising: a cylindrical can; an electrode assembly received in the cylindrical can; and a cap assembly for sealing the cylindrical can, wherein: the cap assembly comprises a top plate having a notch formed thereon, a support plate disposed in close contact with a lower surface of the top plate and including a first through-hole formed through the center thereof, and a bottom plate electrically connected with the electrode assembly and connected to the lower surface of the top plate through the first through-hole; and the support plate has a strength greater than a strength of the top plate.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Dae Kyu KIM, Sung Gwi KO, Shin Jung KIM, Byoung Min CHUN
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Publication number: 20240098048Abstract: A method for displaying a message in a messenger service by a user terminal is proposed. The method may include receiving the message from a server. The method may also include receiving a mask command for the message from the server when text information extracted from the message satisfies a preset condition. The method may further include displaying a mask message corresponding to the message in a chat room of the messenger service based on the mask command.Type: ApplicationFiled: September 8, 2023Publication date: March 21, 2024Inventors: Dae Won YOON, Ki Yong SHIM, Eun Jung KO, Doo Won LEE, Ji Sun LEE
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Publication number: 20240087947Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
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Patent number: 11921561Abstract: For a neural network inference circuit that executes a neural network including multiple computation nodes at multiple layers for which data is stored in a plurality of memory banks, some embodiments provide a method for dynamically putting memory banks into a sleep mode of operation to conserve power. The method tracks the accesses to individual memory banks and, if a certain number of clock cycles elapse with no access to a particular memory bank, sends a signal to the memory bank indicating that it should operate in a sleep mode. Circuit components involved in dynamic memory sleep, in some embodiments, include a core RAM pipeline, a core RAM sleep controller, a set of core RAM bank select decoders, and a set of core RAM memory bank wrappers.Type: GrantFiled: May 27, 2022Date of Patent: March 5, 2024Assignee: PERCEIVE CORPORATIONInventors: Jung Ko, Kenneth Duong, Steven L. Teig
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Publication number: 20240070225Abstract: Some embodiments provide an IC for implementing a machine-trained network with multiple layers. The IC includes a set of circuits to compute a dot product of (i) a first number of input values computed by other circuits of the IC and (ii) a set of predefined weight values, several of which are zero, with a weight value for each of the input values. The set of circuits includes (i) a dot product computation circuit to compute the dot product based on a second number of inputs and (ii) for each input value, at least two sets of wires for providing the input value to at least two of the dot product computation circuit inputs. The second number is less than the first number. Each input value with a corresponding weight value that is not equal to zero is provided to a different one of the dot product computation circuit inputs.Type: ApplicationFiled: October 27, 2023Publication date: February 29, 2024Inventors: Kenneth Duong, Jung Ko, Steven L. Teig
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Patent number: 11916076Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.Type: GrantFiled: June 29, 2020Date of Patent: February 27, 2024Assignee: Adeia Semiconductor Inc.Inventors: Javier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Patent number: 11917148Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.Type: GrantFiled: February 8, 2022Date of Patent: February 27, 2024Assignees: Electronics And Telecommunications Research Institute, Industry-University Cooperation Foundation Korea Aerospace University, Hanbat National University Industry-Academic Cooperation FoundationInventors: Jin-Ho Lee, Jung-Won Kang, Hyunsuk Ko, Sung-Chang Lim, Dong-San Jun, Ha-Hyun Lee, Seung-Hyun Cho, Hui-Yong Kim, Hae-Chul Choi, Dae-Hyeok Gwon, Jae-Gon Kim, A-Ram Back
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Publication number: 20240062054Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network. The method loads a first set of inputs into an input buffer and computes a first dot product between the first set of inputs and a set of weights. The method shifts the first set of inputs in the buffer while loading a second set of inputs into the buffer such that a first subset of the first set of inputs is removed from the buffer, a second subset of the first set of inputs is moved to new locations in the buffer, and a second set of inputs are loaded into locations in the buffer vacated by the shifting. The method computes a second dot product between (i) the second set of inputs and the second subset of the first set of inputs and (ii) the set of weights.Type: ApplicationFiled: October 27, 2023Publication date: February 22, 2024Inventors: Kenneth Duong, Jung Ko, Steven L. Teig
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Publication number: 20240046081Abstract: Some embodiments provide a neural network inference circuit for executing a neural network that includes multiple layers of computation nodes. At least a subset of the layers include non-convolutional layers. The neural network inference circuit includes multiple cores with memories that store input values for the layers. The cores are grouped into multiple clusters. For each cluster, the neural network inference circuit includes a set of processing circuits for receiving input values from the cores of the cluster and executing the computation nodes of the non-convolutional layers.Type: ApplicationFiled: October 8, 2023Publication date: February 8, 2024Inventors: Jung Ko, Kenneth Duong, Steven L. Teig
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Patent number: 11886979Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network. The method loads a first set of inputs into an input buffer and computes a first dot product between the first set of inputs and a set of weights. The method shifts the first set of inputs in the buffer while loading a second set of inputs into the buffer such that a first subset of the first set of inputs is removed from the buffer, a second subset of the first set of inputs is moved to new locations in the buffer, and a second set of inputs are loaded into locations in the buffer vacated by the shifting. The method computes a second dot product between (i) the second set of inputs and the second subset of the first set of inputs and (ii) the set of weights.Type: GrantFiled: March 15, 2019Date of Patent: January 30, 2024Assignee: PERCEIVE CORPORATIONInventors: Kenneth Duong, Jung Ko, Steven L. Teig
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Patent number: 11855950Abstract: A method of providing information on a social networking service (SNS) activity to a chatroom, performed by a user terminal, includes: transmitting, to a server, an SNS request for each of a plurality of anonymous profiles created to be interlinked with an account of a user for an instant messaging service (IMS); displaying information on an SNS activity performed through a first anonymous profile selected by the user in correspondence with a chatroom in which the user participates in the IMS, from among the plurality of anonymous profiles, in the chatroom; receiving an input of changing a profile of the user, selected corresponding to the to chatroom, from the first anonymous profile to a second anonymous profile; and displaying information on an SNS activity performed through the second anonymous profile in the chatroom.Type: GrantFiled: December 9, 2022Date of Patent: December 26, 2023Assignee: KAKAO CORP.Inventors: Ji Sun Lee, Hyun Young Park, Seong Mi Lim, Young Min Park, Doo Won Lee, Eun Jung Ko, Jae Lin Lee, Kwang Hui Lim, Ki Yong Shim, Sun Ho Choi, Kwang Hoon Choi, Hwa Young Lee, Jae Gil Lee, Kyong Rim Kim, Soo Min Cho
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Publication number: 20230395544Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.Type: ApplicationFiled: June 22, 2023Publication date: December 7, 2023Inventors: Javier A. DeLaCruz, Belgacem Haba, Jung Ko
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Patent number: D1017611Type: GrantFiled: June 26, 2023Date of Patent: March 12, 2024Assignee: Samsung Display Co., Ltd.Inventors: Ho Jung Lee, Kyung Hyun Ko, Yong Woo Koo, Jun Il Kwon, Pablo Kim, Young-Su Kim, Jun Woo Kim, Hoon Kim, Hye Suk An, Hyun Joo Lee, Ki Ho Lim