Patents by Inventor Jung-Kuo Tu
Jung-Kuo Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220411260Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
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Patent number: 11516596Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.Type: GrantFiled: October 30, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Chu Lin, Yi-Chuan Teng, Jung-Kuo Tu
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Publication number: 20220367378Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Publication number: 20220340407Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chuan TENG, Ching-Kai SHEN, Jung-Kuo TU, Wei-Cheng SHEN, Xin-Hua HUANG, Wei-Chu LIN
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Publication number: 20220340408Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
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Patent number: 11462478Abstract: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.Type: GrantFiled: May 30, 2019Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20220141596Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: WEI-CHU LIN, YI-CHUAN TENG, JUNG-KUO TU
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Patent number: 11276670Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.Type: GrantFiled: April 17, 2020Date of Patent: March 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Teng, Victor Chiang Liang, Jung-Kuo Tu, Ching-Kai Shen
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Publication number: 20210327852Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chuan Teng, Victor Chiang Liang, Jung-Kuo Tu, Ching-Kai Shen
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Patent number: 11097941Abstract: A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.Type: GrantFiled: April 29, 2019Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsien Chang, Tzu-Heng Wu, Chun-Ren Cheng, Shih-Wei Lin, Jung-Kuo Tu
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Publication number: 20210206627Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Patent number: 10961114Abstract: The present disclosure provides a semiconductor structure, including a sensing substrate, a capping substrate over the sensing substrate, the capping substrate having a first surface facing toward the sensing substrate and a second surface facing away from the sensing substrate, wherein the capping substrate comprises a through hole extending from the first surface to the second surface, a spacer between the sensing substrate and the capping substrate, the spacer, the sensing substrate, and the capping substrate forming a cavity connecting with the through hole, and a sealing structure at the second surface and aligning with the through hole, wherein the sealing structure comprises a metal layer and a dielectric layer.Type: GrantFiled: May 30, 2019Date of Patent: March 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20200377362Abstract: The present disclosure provides a semiconductor structure, including a sensing substrate, a capping substrate over the sensing substrate, the capping substrate having a first surface facing toward the sensing substrate and a second surface facing away from the sensing substrate, wherein the capping substrate comprises a through hole extending from the first surface to the second surface, a spacer between the sensing substrate and the capping substrate, the spacer, the sensing substrate, and the capping substrate forming a cavity connecting with the through hole, and a sealing structure at the second surface and aligning with the through hole, wherein the sealing structure comprises a metal layer and a dielectric layer.Type: ApplicationFiled: May 30, 2019Publication date: December 3, 2020Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Publication number: 20200381366Abstract: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.Type: ApplicationFiled: May 30, 2019Publication date: December 3, 2020Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Patent number: 10510912Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.Type: GrantFiled: December 17, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C. S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
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Publication number: 20190256347Abstract: A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.Type: ApplicationFiled: April 29, 2019Publication date: August 22, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsien CHANG, Tzu-Heng WU, Chun-Ren CHENG, Shih-Wei LIN, Jung-Kuo TU
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Publication number: 20190140112Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Cheng San Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
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Patent number: 10273140Abstract: A substrate structure for a micro electro mechanical system (MEMS) device, a semiconductor structure and a method for fabricating the same are provided. In various embodiments, the substrate structure for the MEMS device includes a substrate, the MEMS device, and an anti-stiction layer. The MEMS device is over the substrate. The anti-stiction layer is on a surface of the MEMS device, and includes amorphous carbon, polytetrafluoroethene, hafnium oxide, tantalum oxide, zirconium oxide, or a combination thereof.Type: GrantFiled: January 16, 2015Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsien Chang, Tzu-Heng Wu, Chun-Ren Cheng, Shih-Wei Lin, Jung-Kuo Tu
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Patent number: 10269586Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.Type: GrantFiled: February 13, 2015Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bruce C. S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
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Patent number: 10164133Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.Type: GrantFiled: July 31, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh