Patents by Inventor Jung-Kuo Tu
Jung-Kuo Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250123450Abstract: Some embodiments relate to an integrated circuit (IC) device that includes a first substrate including an optical lens at a frontside surface of the first substrate, an electrical IC structure disposed proximate a backside surface of the first substrate, and a photonic IC structure disposed proximate a backside surface of the electrical IC structure. The photonic IC structure includes a second substrate providing a backside surface of the photonic IC structure; a photodetector, a grating coupler, and an inverse grating coupler disposed over a frontside surface of the second substrate; and a reflector disposed at a frontside surface of the photonic IC structure. The grating coupler and the inverse grating coupler are configured to direct light from the optical lens and the backside surface of the second substrate, respectively, to the photodetector. The reflector is configured to direct light from the inverse grating coupler back to the inverse grating coupler.Type: ApplicationFiled: October 17, 2023Publication date: April 17, 2025Inventors: Xin-Hua Huang, Kuo-Hao Lee, Jung-Kuo Tu, Kejun Xia, Tse-En Chang
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Patent number: 12202724Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.Type: GrantFiled: July 27, 2023Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20240402441Abstract: A photonic package includes an optical die and an electronic die. The optical die has a first side and a second side opposite to the first side. The optical die includes a first grating coupler, a second grating coupler separated from the first grating coupler and an interconnect structure disposed over the first side. The first grating coupler includes a plurality of first segments disposed over the first side, and the second grating coupler includes a plurality of second segments disposed over the first side. The first segments and the second segments include a same material. The interconnect structure is disposed between the electronic die and the optical die. The optical die and the electronic die are electrically connected to each other through the interconnect structure. The first segments are in contact with the interconnect structure, and the second segments are separated from the interconnect structure.Type: ApplicationFiled: May 30, 2023Publication date: December 5, 2024Inventors: Kuo-Hao LEE, Xin-Hua HUANG, Jung-Kuo TU, Kejun XIA, Tse-En CHANG
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Publication number: 20240286889Abstract: A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
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Patent number: 12074110Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.Type: GrantFiled: July 27, 2022Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Patent number: 12017908Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.Type: GrantFiled: April 23, 2021Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Yi-Chuan Teng
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Patent number: 11851318Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.Type: GrantFiled: April 22, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Xin-Hua Huang, Wei-Chu Lin
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Publication number: 20230399226Abstract: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20230382719Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Publication number: 20230382718Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
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Patent number: 11807520Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.Type: GrantFiled: June 23, 2021Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu
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Patent number: 11772960Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.Type: GrantFiled: March 22, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20220411260Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
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Patent number: 11516596Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.Type: GrantFiled: October 30, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Chu Lin, Yi-Chuan Teng, Jung-Kuo Tu
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Publication number: 20220367378Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
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Publication number: 20220340408Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
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Publication number: 20220340407Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chuan TENG, Ching-Kai SHEN, Jung-Kuo TU, Wei-Cheng SHEN, Xin-Hua HUANG, Wei-Chu LIN
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Patent number: 11462478Abstract: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.Type: GrantFiled: May 30, 2019Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
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Publication number: 20220141596Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: WEI-CHU LIN, YI-CHUAN TENG, JUNG-KUO TU
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Patent number: 11276670Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.Type: GrantFiled: April 17, 2020Date of Patent: March 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Teng, Victor Chiang Liang, Jung-Kuo Tu, Ching-Kai Shen