Patents by Inventor Jung-Kuo Tu

Jung-Kuo Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9159852
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C. S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Patent number: 9056762
    Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Jung-Kuo Tu, Chen-Chih Fan
  • Publication number: 20150162220
    Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.
    Type: Application
    Filed: February 13, 2015
    Publication date: June 11, 2015
    Inventors: Bruce C.S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
  • Publication number: 20150104895
    Abstract: A method for forming an integrated circuit having Micro-electromechanical Systems (MEMS) includes forming at least two recesses into a first layer, forming at least two recesses into a second layer, the at least two recesses of the second layer being complementary to the recesses of the first layer. An intermediate layer is bonded onto the second layer, the intermediate layer includes through-holes corresponding to the recesses of the second layer. The first layer is bonded to the intermediate layer such that cavities are formed, the cavities to act as operating environments for MEMS devices. The two cavities have different pressures.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Inventors: Shyh-Wei Cheng, Jui-Chun Jui-Chen, Hsi-Cheng Hsu, Chih-Yu Wang, Jung-Kuo Tu, Che-Jung Chu, Yu-Ting Hsu
  • Patent number: 8970023
    Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
  • Patent number: 8916943
    Abstract: An integrated circuit device includes a first layer comprising at least two partial cavities, an intermediate layer bonded to the first layer, the intermediate layer formed to support at least two Micro-electromechanical System (MEMS) devices, and a second layer bonded to the intermediate layer, the second layer comprising at least two partial cavities to complete the at least two partial cavities of the first layer through the intermediate layer to form at least two sealed full cavities. The at least two full cavities have different pressures within.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Wei Cheng, Jui-Chun Weng, Hsi-Cheng Hsu, Chih-Yu Wang, Jung-Kuo Tu, Che-Jung Chu, Yu-Ting Hsu
  • Publication number: 20140264948
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Xin-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20140264698
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Publication number: 20140246708
    Abstract: An integrated circuit device includes a first layer comprising at least two partial cavities, an intermediate layer bonded to the first layer, the intermediate layer formed to support at least two Micro-electromechanical System (MEMS) devices, and a second layer bonded to the intermediate layer, the second layer comprising at least two partial cavities to complete the at least two partial cavities of the first layer through the intermediate layer to form at least two sealed full cavities. The at least two full cavities have different pressures within.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Shyh-Wei Cheng, Jui-Chun Weng, Hsi-Cheng Hsu, Chih-Yu Wang, Jung-Kuo Tu, Che-Jung Chu, Yu-Ting Hsu
  • Publication number: 20140213008
    Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bruce C.S. Chou, Jung-Kuo Tu, Chen-Chih Fan
  • Patent number: 8748999
    Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Jung-Kuo Tu, Chen-Chih Fan
  • Publication number: 20130277771
    Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bruce C.S. Chou, Jung-Kuo Tu, Chen-Chih Fan