Patents by Inventor Jung-Sheng Hoei

Jung-Sheng Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device program window adjustment
    Patent number: 8307152
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE
    Publication number: 20120275233
    Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung-Sheng Hoei, Jonathan Pabustan
  • Expanded programming window for non-volatile multilevel memory cells
    Patent number: 8289776
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung Sheng Hoei, Frankie F. Roohparvar
  • Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and counters, and sensing methods thereof
    Patent number: 8289779
    Abstract: The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An output of a second counter can be provided to sensing circuitry coupled to a sense line of the memory cell. Conduction of the sense line in response to the ramping voltage can be sensed, and an output value of the second counter can be determined in response to the sensed conduction of the sense line.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jung-Sheng Hoei
  • Data conditioning to improve flash memory reliability
    Patent number: 8281061
    Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
    Patent number: 8274833
    Abstract: A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. A read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Methods of operating memories including characterizing memory cell signal lines
    Patent number: 8254180
    Abstract: Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jung-Sheng Hoei, Jonathan Pabustan, Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8254182
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Non-volatile multilevel memory cells with data read of reference cells
    Patent number: 8243513
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: August 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung Sheng Hoei, Frankie F. Roohpavar
  • Soft landing for desired program threshold voltage
    Patent number: 8223551
    Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung-Sheng Hoei, Jonathan Pabustan
  • METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES
    Publication number: 20120159277
    Abstract: Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, wherein each ramped voltage signal segment has a different start voltage and a different end voltage than the other ramped voltage signal segments.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Inventor: Jung-Sheng Hoei
  • MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE
    Publication number: 20120113723
    Abstract: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT
    Publication number: 20120117313
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Inventors: Vishal SARIN, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • Apparatus and method for increasing data line noise tolerance
    Patent number: 8174919
    Abstract: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Chia-Shing Jason Yu, Jung-Sheng Hoei, Vishal Sarin
  • Methods of erase verification for a flash memory device
    Patent number: 8169832
    Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Dzung Nguyen, Jonathan Pabustan, Jung Sheng Hoei, Jason Guo, William Saiki
  • REDUCING NOISE IN SEMICONDUCTOR DEVICES
    Publication number: 20120069675
    Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 22, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei
  • Memory device program window adjustment
    Patent number: 8117375
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • M+N bit programming and M+L bit read for M bit memory cells
    Patent number: 8111550
    Abstract: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 7, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS
    Publication number: 20120030529
    Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 2, 2012
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
    Patent number: 8107296
    Abstract: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar