Patents by Inventor Jung-Sheng Hoei

Jung-Sheng Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF ERROR-BASED READ DISTURB MITIGATION AND MEMORY DEVICES UTILIZING THE SAME
    Publication number: 20180374549
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • APPARATUSES AND METHODS TO CONTROL MEMORY OPERATIONS ON BUFFERS
    Publication number: 20180349029
    Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
  • PARTIALLY WRITTEN BLOCK TREATMENT
    Publication number: 20180210653
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • REDUNDANT ARRAY OF INDEPENDENT NAND FOR A THREE-DIMENSIONAL MEMORY ARRAY
    Publication number: 20170249211
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • Three dimensional memory control circuitry
    Patent number: 9620229
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Data conditioning to improve flash memory reliability
    Patent number: 9471425
    Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20160196879
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: October 29, 2015
    Publication date: July 7, 2016
    Inventors: MARK HELM, JUNG SHENG HOEI, AARON YIP, DZUNG NGUYEN
  • Three dimensional memory control circuitry
    Patent number: 9202536
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Reducing noise in semiconductor devices
    Patent number: 9196370
    Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei
  • Sensing memory cells
    Patent number: 9093162
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung Sheng Hoei, Frankie Roohparvar, Giulio-Giuseppe Marotta
  • Coarse and fine programming in a solid state memory
    Patent number: 8995182
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Analog sensing of memory cells in a solid-state memory device
    Patent number: 8976582
    Abstract: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Programming based on controller performance requirements
    Patent number: 8953374
    Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 10, 2015
    Assignee: Mircon Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY
    Publication number: 20140298088
    Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 2, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device
    Patent number: 8787103
    Abstract: An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Soft landing for desired program threshold voltage
    Patent number: 8773912
    Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung-Sheng Hoei, Jonathan Pabustan
  • Data conditioning to improve flash memory reliability
    Patent number: 8762629
    Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20140146612
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: March 26, 2012
    Publication date: May 29, 2014
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits
    Patent number: 8737127
    Abstract: A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Jonathan Pabustan, Frankie F. Roohparvar
  • Memory device program window adjustment
    Patent number: 8713246
    Abstract: In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei