Patents by Inventor Jung-Sheng Hoei

Jung-Sheng Hoei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory devices with read level calibration
    Patent number: 10510422
    Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
  • NAND TEMPERATURE DATA MANAGEMENT
    Publication number: 20190333585
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 31, 2019
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • APPARATUSES AND METHODS TO CONTROL MEMORY OPERATIONS ON BUFFERS
    Publication number: 20190332284
    Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
  • Temperature sensitive NAND programming
    Patent number: 10446237
    Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Jung Sheng Hoei, Harish Reddy Singidi, Ting Luo, Ankit Vashi
  • Partially written block treatment
    Patent number: 10423350
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • PARTIALLY WRITTEN BLOCK TREATMENT
    Publication number: 20190286328
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • METHODS OF ERROR-BASED READ DISTURB MITIGATION AND MEMORY DEVICES UTILIZING THE SAME
    Publication number: 20190272881
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Application
    Filed: May 18, 2019
    Publication date: September 5, 2019
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • REDUNDANT ARRAY OF INDEPENDENT NAND FOR A THREE-DIMENSIONAL MEMORY ARRAY
    Publication number: 20190258544
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • Apparatuses and methods to control memory operations on buffers
    Patent number: 10372353
    Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
  • Partially written block treatment
    Patent number: 10359963
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • NAND temperature data management
    Patent number: 10354732
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Methods of error-based read disturb mitigation and memory devices utilizing the same
    Patent number: 10340016
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • Redundant array of independent NAND for a three-dimensional memory array
    Patent number: 10318378
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • LAST WRITTEN PAGE SEARCHING
    Publication number: 20190155744
    Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh, Michael G. Miller, Xiaoxiao Zhang, Jung Sheng Hoei
  • SLC PAGE READ
    Publication number: 20190130983
    Abstract: NAND memory devices, are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Inventors: Harish Singidi, Scott Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
  • NAND TEMPERATURE DATA MANAGEMENT
    Publication number: 20190066792
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • MEMORY DEVICES WITH READ LEVEL CALIBRATION
    Publication number: 20190043592
    Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.
    Type: Application
    Filed: September 10, 2018
    Publication date: February 7, 2019
    Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
  • MEMORY DEVICES WITH READ LEVEL CALIBRATION
    Publication number: 20190043590
    Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 7, 2019
    Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
  • Memory devices with read level calibration
    Patent number: 10199111
    Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
  • METHODS OF ERROR-BASED READ DISTURB MITIGATION AND MEMORY DEVICES UTILIZING THE SAME
    Publication number: 20180374549
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi