Abstract: Disclosed is a technique for switching from a master node to a secondary node in a communication system. A method of a first communication node may comprise: adding the first communication node as a primary secondary cell (PSCell) to a second communication node through dual connectivity (DC); generating a first user plane path for smart dynamic switching (SDS) and a first instance for supporting the first user plane path according to a request from the second communication node; transmitting information on the first user plane path and the first instance to a terminal; receiving user data based on the first user plane path from the terminal as the first instance; and transmitting the user data to a core network using the first user plane path.

Abstract: A method for treating a cell damage-related disease, including administering a composition to a subject in need thereof. The composition contains, as an active ingredient, one or more selected from the group consisting of stem cells genetically engineered to overexpress a carcinoembryonic antigen-related cell adhesion molecule (CEACAM) family protein, cells differentiated from the stem cells, and components derived from the stem cells.

Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.

Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.

Abstract: A display device includes a substrate, a transistor on the substrate, a pixel electrode connected to the transistor, a bank layer disposed on the pixel electrode and defining a pixel opening overlapping the pixel electrode, an emission layer in the pixel opening, a common electrode on the emission layer and the bank layer, an encapsulation layer on the common electrode, a sensing electrode on the encapsulation layer, a first insulating layer disposed on the encapsulation layer and overlapping the pixel opening, a second insulating layer on the first insulating layer, and a third insulating layer surrounding the first insulating layer. A refractive index of the first insulating layer, a refractive index of the second insulating layer, and a refractive index of the third insulating layer are different from one another, and the refractive index of the first insulating layer is greater than the refractive index of the third insulating layer.

Abstract: A fingerprint sensor including: a substrate; a light sensing element that includes a sensing electrode disposed on the substrate, a semiconductor layer disposed on the sensing electrode, and a common electrode disposed on the semiconductor layer; a light-blocking conductive layer disposed on the common electrode and including light transmitting holes; and a light guide unit disposed on the light-blocking conductive layer.

Abstract: A memory device may include a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The memory device may determine, when programming a first memory cell among the plurality of memory cells to a target program state, a precharge time based on a number of times that a program voltage is applied to a first word line connected to the first memory cell among the plurality of word lines, and may precharge the plurality of bit lines during the precharge time when executing a verify operation on the first memory cell.

Abstract: Disclosed herein are an apparatus and method for an adaptive checkpoint in intermittent computing. The apparatus for an adaptive checkpoint in intermittent computing includes memory in which at least one program is recorded and a processor for executing the program. The program may perform statically setting locations at which checkpoints are to be performed at compile time of program code and dynamically determining whether to perform the checkpoints depending on energy-harvesting conditions at runtime of the program code.

Abstract: A light-emitting diode (LED) lamp for a vehicle and a method of manufacturing the same use MID and magnetic induction technologies. The LED lamp includes a LED module, a housing accommodating the LED module, and a molded interconnect device (MID) electrode formed on a surface of the housing. The LED module may be mounted on the MID electrode by soldering using magnetic induction heating, the housing may be an injection molded product, and the MID electrode may be formed on the housing using a MID process.

Abstract: Embodiments of the present disclosure relate to a memory device and an operating method of the memory device. According to embodiments of the present disclosure, a memory device may include a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, wherein the memory device may determine, when programming a first memory cell among the plurality of memory cells to a target program state, a precharge time based on a number of times that a program voltage is applied to a first word line connected to the first memory cell among the plurality of word lines, and may precharge the plurality of bit lines during the precharge time when executing a verify operation on the first memory cell.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a memory device including a plurality of memory blocks, and a memory controller configured to: manage an accumulated erase count value and an open block erase count value of each of the plurality of memory blocks, and select a target memory block on which a program operation is to be performed based on the accumulated erase count value and the open block erase count value of each of the plurality of memory blocks.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, control logic, and a bit flip sensor. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to receive program data, and perform a program operation on selected memory cells among the plurality of memory cells, based on the program data. The bit flip sensor is configured to receive the program data from the read/write circuit, and determine whether a bit flip has occurred in the program data. The control logic is configured to control the program operation of the read/write circuit, and generate program status information, based on a determination result of the bit flip sensor.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a memory device including a plurality of memory blocks, and a memory controller configured to: manage an accumulated erase count value and an open block erase count value of each of the plurality of memory blocks, and select a target memory block on which a program operation is to be performed based on the accumulated erase count value and the open block erase count value of each of the plurality of memory blocks.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, control logic, and a bit flip sensor. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to receive program data, and perform a program operation on selected memory cells among the plurality of memory cells, based on the program data. The bit flip sensor is configured to receive the program data from the read/write circuit, and determine whether a bit flip has occurred in the program data. The control logic is configured to control the program operation of the read/write circuit, and generate program status information, based on a determination result of the bit flip sensor.

Abstract: There are provided a memory system and an operating method of the memory system. The memory system includes: a memory device including a plurality of semiconductor memories; and a controller for controlling the memory device to perform a bad block detection operation on free blocks among a plurality of memory blocks included in a selected semiconductor memory among the plurality of semiconductor memories. The controller selects, as a target memory block, memory blocks adjacent to a bad bock detected based on a result of the bad block detection operation, and controls the memory device to perform the bad block detection operation on the target memory block.

Abstract: A method of handling a page fault occurring in a non-volatile main memory system including analyzing a pattern of occurrence of the page fault based on the page fault when the page fault occurs, setting the number of pages to be consecutively processed based on analysis result of the analyzing, and consecutively processing as many pages as the number may be provided.

Abstract: The present invention relates to a magnet-integrated-type torque angle sensor module and, more particularly, to a torque angle sensor module that integrates magnets used for detecting steering direction, steering angle, torque, and steering speed and simplifies component configuration, capable of minimizing the rate of defects during assembly, improving disassembling ability, and inducing performance stabilization.

Abstract: An electronic device and a method a provided. The electronic device includes a first surface, a second surface opposite to the first surface, and a side surface that surrounds at least part of a space between the first and second surfaces; a Radio Frequency (RF) communication circuit; an antenna radiator that forms at least part of at least one of the first surface, the second surface, and the side surface and is connected to the RF communication circuit; a sensor that detects whether an external object contacts the antenna radiator; a switching circuit connected to the antenna radiator and the sensor; and a processor configured to receive a first value from the sensor when the antenna radiator and the sensor are connected to each other and to receive a second value from the sensor when the antenna radiator and the sensor are separated from each other.

Abstract: A memory mapping management method for a system using nonvolatile memory (NVM) as main memory, including receiving a request to cancel a memory mapping, determining whether the memory mapping is a mapping of a file based on meta data relating to the memory mapping, separately storing the meta data when the memory mapping is the mapping of the file, and cancelling the memory mapping when the memory mapping is not the mapping of the file may be provided. Further, the memory mapping management method may include receiving a memory mapping request, searching for a memory mapping for a file in a memory mapping storage space when a requested memory mapping is a mapping of the file, and reusing a searched memory mapping found during the search when a region of the searched memory mapping includes a region required by the requested memory mapping in a virtual address space.

Abstract: A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.