Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal layers connected to the first region of the redistribution layer through the plurality of first openings, respectively.

Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

Abstract: A printed circuit board includes an internal insulating layer, an internal conductive pattern layer disposed on the internal insulating layer and including a line portion and a bonding pad portion, and an external insulating layer disposed on the internal conductive pattern layer and the internal insulating layer and having an accommodation groove extending therethrough to expose the bonding pad portion. The bonding pad portion includes a connection pattern extending from the line portion of the internal conductive pattern layer embedded in the external insulating layer, and exposed to the accommodation groove; a land pattern disposed closer to a center portion of the accommodation groove than the connection pattern; and a dam pattern connecting the connection pattern and the land pattern, in which a line width of the dam pattern is narrower than a line width of the land pattern.

Abstract: Disclosed is a dike for semiconductor/LCD manufacturing and processing equipment, in which a plurality of straight blocks and a plurality of corner blocks, having a predetermined height, are engaged to form a polygonal-shaped fence having a predetermined area, and molten epoxy is injected to a predetermined height in the space within the fence and solidified.

Abstract: A printed circuit board includes an internal insulating layer, an internal conductive pattern layer disposed on the internal insulating layer and including a line portion and a bonding pad portion, and an external insulating layer disposed on the internal conductive pattern layer and the internal insulating layer and having an accommodation groove extending therethrough to expose the bonding pad portion. The bonding pad portion includes a connection pattern extending from the line portion of the internal conductive pattern layer embedded in the external insulating layer, and exposed to the accommodation groove; a land pattern disposed closer to a center portion of the accommodation groove than the connection pattern; and a dam pattern connecting the connection pattern and the land pattern, in which a line width of the dam pattern is narrower than a line width of the land pattern.

Abstract: Disclosed is a dike for semiconductor/LCD manufacturing and processing equipment, in which a plurality of straight blocks and a plurality of corner blocks, having a predetermined height, are engaged to form a polygonal-shaped fence having a predetermined area, and molten epoxy is injected to a predetermined height in the space within the fence and solidified.

Abstract: A method for manufacturing a printed circuit board includes forming a through hole in an insulating layer of the printed circuit board, filling the through hole by plating to form a plating layer on the insulating layer, and removing the plating layer from the insulating layer; and forming a circuit pattern on the insulating layer.

Abstract: A printed circuit board includes an insulating layer having a first surface and a second surface opposing the first surface; and a first wiring including a first line pattern disposed on the first surface of the insulating layer, and a plurality of first protruding patterns penetrating a portion of the insulating layer from the first surface and connected to the first line pattern, respectively, such that the plurality of first protruding patterns overlap the first line pattern in a plan view of the printed circuit board.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.

Abstract: A vacuum dryer including a chamber configured to provide an interior space, support pins in the interior space proximate to a bottom of the chamber, a power supply configured to supply power to the support pins, and a pump coupled to the interior space in the chamber.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal bumps connected to the first region of the redistribution layer through the plurality of first openings, respectively.

Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: An optical measuring method includes generating a Bessel beam, filtering the Bessel beam to generate a focused Bessel beam, vertically irradiating the focused Bessel beam onto a substrate in which an opening is formed, and detecting light reflected from the substrate to obtain an image of a bottom surface of the opening.

Abstract: A frequency locked loop is disclosed. The disclosed frequency locked loop may include: a voltage-controlled oscillator configured to output a LO signal; a mixer configured to mix an RF signal with the LO signal to output an IF signal; a first IF path part configured to transfer the IF signal; a second IF path part configured to transfer the IF signal; and an error amplifier configured to receive output signals of the first IF path part and output signals of the second IF part as input, where the voltage-controlled oscillator adjusts a frequency of the LO signal based on an output signal of the error amplifier, the first IF path part has the conversion gain decreased according to an increase in the frequency of the IF signal, and the second IF path part has the conversion gain increased according to an increase in the frequency of the IF signal.

Abstract: Provided is a virtual currency generation apparatus including a blockchain generator configured to generate a blockchain including a virtual currency that is generated based on a credit limit of a consumer and to update the blockchain based on payment details; an account manager configured to manage multi-signatures of a plurality of accounts sharing the blockchain; and a transaction generator configured to store a transaction condition corresponding to each of the plurality of accounts and to proceed with a payment using the virtual currency based on the transaction condition.

Abstract: Disclosed herein is an ultrasonic diagnostic apparatus. The ultrasonic diagnostic apparatus includes an ultrasound probe provided with an array having at least one transducer; a display configured to display an image captured by the array; a body provided with a controller configured to, when at least one image is selected by a user among a plurality of images captured according to a rotation angle of the array, control a rotation angle of the array to allow the selected image to be displayed on the display.