Patents by Inventor Jung-Suk Goo
Jung-Suk Goo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8818785Abstract: A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.Type: GrantFiled: November 3, 2011Date of Patent: August 26, 2014Assignees: GLOBALFOUNDRIES Inc., Advanced Micro Devices, Inc.Inventors: Jung-Suk Goo, Ciby Thuruthiyil, Venkat Ramasubramanian, John Faricelli
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Patent number: 8618592Abstract: A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.Type: GrantFiled: April 29, 2011Date of Patent: December 31, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Hyun-Jin Cho, Sang H. Dhong, Jung-Suk Goo, Gurupada Mandal
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Patent number: 8586981Abstract: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or more of the at least two semiconductor body contacts forms a direct electrical contact with the doped halo, thereby increasing current flow to the doped halo to facilitate measuring body-effect in the SOI transistor test structure.Type: GrantFiled: October 5, 2006Date of Patent: November 19, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Qiang Chen, Jung-Suk Goo
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Publication number: 20130117002Abstract: A tucked transistor device has a diffusion region defined in a semiconductor layer, a switching gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode. A method includes receiving a netlist having an entry for the tucked transistor device in a computing apparatus, the entry defining parameters associated with the switching gate electrode and the diffusion region, receiving a device parameter file including at least a gate bounded junction capacitance parameter that includes a junction capacitance bounded by the switching gate electrode modified to include a contribution of the floating gate electrode to a gate bounded junction capacitance of the tucked transistor device. Operation of the tucked transistor device is simulated in the computing apparatus using a transistor device model and the netlist.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicants: ADVANCED MICRO DEVICES, INC., GLOBALFOUNDRIES INC.Inventors: Jung-Suk Goo, Ciby Thuruthiyil, Venkat Ramasubramanian, John Faricelli
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Publication number: 20130117001Abstract: A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicants: ADVANCED MICRO DEVICES, INC., GLOBALFOUNDRIES INC.Inventors: Jung-Suk Goo, Ciby Thuruthiyil, Venkat Ramasubramanian, John Faricelli
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Patent number: 8293606Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.Type: GrantFiled: December 20, 2010Date of Patent: October 23, 2012Assignee: GLOBALFOUNDARIES, Inc.Inventors: Sriram Madhavan, Qiang Chen, Darin A. Chan, Jung-Suk Goo
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Patent number: 8275596Abstract: According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example. sizes and locations of semiconductor devices on semiconductor dies.Type: GrantFiled: December 8, 2006Date of Patent: September 25, 2012Assignee: Globalfoundries Inc.Inventors: Vineet Wason, Jung-Suk Goo, Zhi-Yuan Wu, Ciby T. Thuruthiyil
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Patent number: 8099269Abstract: The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation.Type: GrantFiled: October 9, 2007Date of Patent: January 17, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Rasit O. Topaloglu, Jung-Suk Goo
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Publication number: 20110204429Abstract: A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Hyun-Jin CHO, Sang H. DHONG, Jung-Suk GOO, Gurupada MANDAL
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Patent number: 7977172Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.Type: GrantFiled: December 8, 2008Date of Patent: July 12, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Hyun-Jin Cho, Sang H. Dhong, Jung-Suk Goo, Gurupada Mandal
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Patent number: 7932103Abstract: An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof.Type: GrantFiled: February 28, 2007Date of Patent: April 26, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Niraj Subba, Jung-Suk Goo
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Publication number: 20110086484Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Sriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
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Patent number: 7923785Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.Type: GrantFiled: August 18, 2003Date of Patent: April 12, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Qi Xiang, Boon-Yong Ang, Jung-Suk Goo
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Patent number: 7880229Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.Type: GrantFiled: October 18, 2007Date of Patent: February 1, 2011Assignee: GlobalFoundries Inc.Inventors: Sriram Madhavan, Qiang Chen, Darin A. Chan, Jung-Suk Goo
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Patent number: 7761823Abstract: According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.Type: GrantFiled: May 15, 2007Date of Patent: July 20, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Jung-Suk Goo, Qiang Chen
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Publication number: 20100144106Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Hyun-Jin CHO, Sang H. DHONG, Jung-Suk GOO, Gurupada MANDAL
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Patent number: 7732336Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.Type: GrantFiled: May 5, 2008Date of Patent: June 8, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Qi Xiang, James N. Pan, Jung-Suk Goo
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Publication number: 20090101976Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Sriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
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Publication number: 20090094013Abstract: The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Rasit O. TOPALOGLU, Jung-Suk Goo
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Patent number: 7462549Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.Type: GrantFiled: January 12, 2004Date of Patent: December 9, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, James N. Pan, Jung-Suk Goo