Patents by Inventor Jung Wang
Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11844288Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.Type: GrantFiled: February 4, 2021Date of Patent: December 12, 2023Assignee: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang
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Publication number: 20230380742Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: ApplicationFiled: July 8, 2022Publication date: November 30, 2023Inventors: Chun-Te HUANG, Kai-Chih PAI, Tsai-Jung WANG, Min-Shian WANG, Yan-Nan LIN, Cheng-Hsu CHEN, Chun-Ming LAI, Ruey-Kai SHEU, Lun-Chi CHEN, Chieh-Liang WU, Chien-Lun LIAO, Ta-Chun HUNG, Chien-Chung HUANG, Chia-Tien HSU, Shang-Feng TSAI
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Publication number: 20230380293Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
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Patent number: 11821234Abstract: A seismic isolation device comprises an isolation support and an inerter unit arranged on the side of the isolation support, the isolation support having an upper plate and a lower plate, the inerter unit having a rotating rod extending to the side of the lower plate and a flywheel linked with the rotating rod, wherein when the upper and lower plates of the present invention undergo relative displacement due to the occurrence of an earthquake, the inerter unit provide an inertance to reduce the displacement reaction, thereby providing better seismic isolation effect.Type: GrantFiled: January 26, 2022Date of Patent: November 21, 2023Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Ting-Yu Hsu, Shiang-Jung Wang
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Patent number: 11817388Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.Type: GrantFiled: June 28, 2022Date of Patent: November 14, 2023Assignee: Innolux CorporationInventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
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Patent number: 11806192Abstract: A guiding system and a guiding method for ultrasound scanning operation are provided. The guiding system includes a handheld guiding device, a display device, an ultrasound scanning device, a prompting device, and a control host. When the handheld guiding device generates a first physical motion, the control host detects the first physical motion and generates navigation prompting information accordingly. The prompting device is suitable for presenting the navigation prompting information to guide the ultrasound scanning device to move to generate a second physical motion. The control host captures an ultrasound image via the ultrasound scanning device and sends the ultrasound image to the display device at a guiding end for display.Type: GrantFiled: October 25, 2021Date of Patent: November 7, 2023Assignee: Industrial Technology Research InstituteInventors: Chien-Ju Li, Peng-Zhi Sun, Yi-Jung Wang, Brian Hsu
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Patent number: 11800812Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.Type: GrantFiled: March 7, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
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Patent number: 11798860Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.Type: GrantFiled: June 10, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pei-Haw Tsao, Chien-Jung Wang
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Patent number: 11770977Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.Type: GrantFiled: October 27, 2020Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jiann-Horng Lin, Kun-Yi Li, Han-Ting Lin, Huan-Just Lin, Chen-Jung Wang, Sin-Yi Yang
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Patent number: 11758821Abstract: A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.Type: GrantFiled: December 8, 2021Date of Patent: September 12, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
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Patent number: 11749570Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-De Ho, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
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Publication number: 20230276715Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
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Patent number: 11731004Abstract: A vertical oscillation auxiliary platform, wherein a drive mechanism drives an upper cover tread board to make vertical up-and-down movements with a transmission mechanism; when the drive mechanism drives a transmission shaft rotate, the transmission shaft drives lower parts of 8-shaped bearing blocks to rotate eccentrically, and upper parts thereof move horizontally; the 8-shaped bearing blocks drive one end of triangular bearing blocks to move horizontally with horizontal transmission rods, and the triangular bearing blocks, without moving a third end, convert horizontal movements at one end to be vertical movements at another end, and drive finally the upper cover tread board to generate stable vertical oscillation, so that singularity and stability of vertical movements of the upper cover tread board can be promised, and more stable and comfortable feeling and passive exercise effects can be gained, without deteriorating the exercise effects and exercise comfort due to additional disorganized lateral moveType: GrantFiled: October 19, 2021Date of Patent: August 22, 2023Assignee: MAIZU INTELLIGENT TECHNOLOGY (SHANGHAI) CO., LTD.Inventors: Shih-jung Wang, Hailong Wang
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Publication number: 20230260315Abstract: Provided is a fingerprint sensing system disposed under a display. The fingerprint sensing system includes a sensor and a controller. The sensor has a plurality of sensing pixels arranged into an array, and the sensing pixels includes at least one functional sensing pixel. The controller is electrically connected to the sensor. The controller calculates an environmental parameter according to a signal obtained by the at least one functional sensing pixel.Type: ApplicationFiled: October 19, 2020Publication date: August 17, 2023Applicant: Egis Technology Inc.Inventors: Tong-Long Fu, Wei Jung Wang
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Publication number: 20230261508Abstract: A power supply including a first conversion circuit, a second conversion circuit, a first output capacitor, a second output capacitor, a first discharge circuit, and a second discharge circuit is provided. The first conversion circuit converts a first alternating current (AC) power to a first direct current (DC) power. The second conversion circuit converts a second AC power to a second DC power. The first output capacitor is configured to store the first DC power. The second output capacitor is configured to store the second DC power. The first discharge circuit provides a first discharge path to discharge the first output capacitor in response to the first DC power being greater than the second DC power. The second discharge circuit provides a second discharge path to discharge the second output capacitor in response to the second DC power being greater than the first DC power.Type: ApplicationFiled: November 9, 2022Publication date: August 17, 2023Inventors: Tzu-Tseng CHAN, Chih-Chiang CHEN, Chuan-Jung WANG
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Publication number: 20230263068Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.Type: ApplicationFiled: April 19, 2023Publication date: August 17, 2023Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
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Publication number: 20230232686Abstract: A display apparatus includes: a base substrate including a display area and a non-display area adjacent to the display area; a first power supply wire in the non-display area, a first power supply voltage being applied to the first power supply wire; a second power supply wire in the non-display area and spaced apart from the first power supply wire, a second power supply voltage being applied to the second power supply wire; and a dam overlapping the first power supply wire and the second power supply wire, having a first height on the first power supply wire, and having a second height greater than the first height between the first power supply wire and the second power supply wire.Type: ApplicationFiled: March 27, 2023Publication date: July 20, 2023Inventors: Young Jin CHO, Joong-Soo MOON, Yang Wan KIM, Soon Jung WANG
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Patent number: 11683991Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.Type: GrantFiled: November 24, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20230178130Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an antiferromagnetic layer, and a magnetic tunnel junction. The antiferromagnetic layer is disposed on the heavy metal layer, and the magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a free layer, a barrier layer, and a pinned layer. The barrier layer is disposed on the free layer, and the pinned layer is disposed on the barrier layer. A film surface shape of the free layer is a rounded rectangle.Type: ApplicationFiled: December 28, 2021Publication date: June 8, 2023Applicant: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang, Fang-Ming Chen
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Publication number: 20230179009Abstract: A charging method with hysteresis includes the steps of: performing a pre-determination process to check whether the battery temperature of a battery cell is higher than or equal to a predetermined temperature; if the battery temperature is higher than or equal to the predetermined temperature, enabling a hysteresis mechanism; Upon the hysteresis mechanism, initially charging the battery cell with a small charging current; performing a first determination process to check whether the battery temperature decreases to a first threshold temperature; if the battery temperature decreases to the first threshold temperature, charging the battery cell with a large charging current; performing a second determination process to check whether the battery temperature increases to a second threshold temperature; and if the battery temperature increases to the second threshold temperature, charging the battery cell with the small charging current.Type: ApplicationFiled: March 21, 2022Publication date: June 8, 2023Inventors: Shuo-Jung CHOU, Chuan-Jung WANG, Chih-Chiang CHEN