Patents by Inventor Jung Wang

Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220337077
    Abstract: A battery module for monitoring and suppressing battery swelling and interacting with a charging device includes a battery cell disposed in a nonconductive housing, a conductive label affixed to the nonconductive housing, a switch, and a controller. The battery cell is charged via a supply voltage from a charging device. The switch is coupled between the battery cell and the conductive label. The controller detects a resistance variation value ?R of the conductive label as result of swelling of the nonconductive housing, and generates a corresponding control voltage. As the resistance of the conductive label increases, the supply voltage may be adjusted downward according to the control voltage. If the resistance variation value ?R conductive label is greater than or equal to a predetermined threshold, the controller closes the switch, and the battery cell may then fully discharge through the conductive label.
    Type: Application
    Filed: October 18, 2021
    Publication date: October 20, 2022
    Inventors: Shuo-Jung CHOU, Chuan-Jung WANG, Chih-Chiang CHEN
  • Publication number: 20220336523
    Abstract: The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting element. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting element is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 20, 2022
    Inventors: Chia-Ting HSIEH, Chien-Fu HUANG, Cheng-Nan YEH, Seok-Lyul LEE, Yung-Hsiang LAN, June-Woo LEE, Sung-Yu SU, Hsien-Chun WANG, Ya-Jung WANG, Hsin-Ying LIN, Yu-Chieh LIN, Yang-En WU
  • Publication number: 20220335887
    Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 20, 2022
    Applicant: Au Optronics Corporation
    Inventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
  • Publication number: 20220336727
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20220336425
    Abstract: The present disclosure provides a light emitting diode component, including a body and a plurality of P-N diode structures. The P-N diode structures are coupled in series and integrated on the body. The P-N diode structures include a plurality of p-type doping layers and a plurality of n-type doping layers. The p-type doping layer of a first P-N diode structure in the P-N diode structures is electrically coupled to the n-type doping layer of a second P-N diode structure in the P-N diode structures.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 20, 2022
    Inventors: June-Woo LEE, Yang-En WU, Sung-Yu SU, Hsien-Chun WANG, Ya-Jung WANG, Chia-Ting HSIEH, Chien-Fu HUANG, Hsin-Ying LIN
  • Publication number: 20220328405
    Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Publication number: 20220328406
    Abstract: The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Publication number: 20220271087
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: HAN-TING LIN, JIANN-HORNG LIN, HSING-HSIANG WANG, HUAN-JUST LIN, SIN-YI YANG, CHEN-JUNG WANG, KUN-YI LI, MENG-CHIEH WEN, LAN-HSIN CHIANG, LIN-TING LIN
  • Publication number: 20220271351
    Abstract: An electronic device for suppressing battery swelling includes a first battery cell, a first conductive label, a second conductive label, a third conductive label, and a BMU (Battery Management Unit). The first battery cell includes a first nonconductive housing. The first conductive label, the second conductive label, and the third conductive label are disposed on the first nonconductive housing. The BMU outputs a charging voltage to the first battery cell. The BMU determines the voltage level of the charging voltage by detecting the states of the first conductive label, the second conductive label, and the third conductive label.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 25, 2022
    Inventors: Shuo-Jung CHOU, Chuan-Jung WANG, Chih-Chiang CHEN
  • Publication number: 20220258933
    Abstract: The present invention relates to a multi-vacuum valve of a vacuum container. The present invention relates to a push button made from one selected from soft synthetic resin and soft silicone, comprising: a protruding annular rim protruding downward from the circumferential direction of the perimeter of a support part; a guide groove for the linear movement of a pressing part, which is recessed downward from a portion at which the outer circumferential end portion of the pressing part and the upper end of a height-varying part are in contact with each other; and a circular airtightness-maintaining rod for vertically moving downward by the pressing of the pressing part. The inflow/outflow of air, due to fine wear or damage caused by the cleaning of an airtight member, can be prevented and the inflow/outflow of air through a fine gap due to the distortion of the airtight member or gas pressure generated from food can be prevented, and thus a food storage period can be extended.
    Type: Application
    Filed: June 25, 2020
    Publication date: August 18, 2022
    Inventors: Soo Jung WANG, Young Bin WANG, Bang Hyang SONG
  • Publication number: 20220251863
    Abstract: A seismic isolation device comprises an isolation support and an inerter unit arranged on the side of the isolation support, the isolation support having an upper plate and a lower plate, the inerter unit having a rotating rod extending to the side of the lower plate and a flywheel linked with the rotating rod, wherein when the upper and lower plates of the present invention undergo relative displacement due to the occurrence of an earthquake, the inerter unit provide an inertance to reduce the displacement reaction, thereby providing better seismic isolation effect.
    Type: Application
    Filed: January 26, 2022
    Publication date: August 11, 2022
    Applicant: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Ting-Yu Hsu, Shiang-Jung Wang
  • Patent number: 11411176
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 11387406
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20220190237
    Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20220175347
    Abstract: A guiding system and a guiding method for ultrasound scanning operation are provided. The guiding system includes a handheld guiding device, a display device, an ultrasound scanning device, a prompting device, and a control host. When the handheld guiding device generates a first physical motion, the control host detects the first physical motion and generates navigation prompting information accordingly. The prompting device is suitable for presenting the navigation prompting information to guide the ultrasound scanning device to move to generate a second physical motion. The control host captures an ultrasound image via the ultrasound scanning device and sends the ultrasound image to the display device at a guiding end for display.
    Type: Application
    Filed: October 25, 2021
    Publication date: June 9, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chien-Ju Li, Peng-Zhi Sun, Yi-Jung Wang, Brian Hsu
  • Publication number: 20220181257
    Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Publication number: 20220149548
    Abstract: A bridge includes a connecting platform, an electrical connector, a wireless communication module, and a processing unit. The electrical connector is disposed on the connecting platform. The wireless communication module is disposed on the connecting platform and configured to receive a wireless signal. The processing unit is configured to: carry out a verification process on information included in the wireless signal; and allow the electrical connector to transmit power when the verification process on the information turned out to be true.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 12, 2022
    Inventors: Yu-Jung Wang, Chen-Hsin Hsu, Zih-Wei Chen
  • Publication number: 20220131070
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
  • Patent number: 11302635
    Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: April 12, 2022
    Assignee: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Patent number: 11298696
    Abstract: The present disclosure provides a reaction cassette for biochemical test. The reaction cassette includes a structural wall, a first flow guiding member and an obstacle member. The structural wall defines a reaction region and a channel region, wherein the reaction region is connected to the channel region. The first flow guiding member is disposed in the channel region, and a first angle between the structural wall and the first flow guiding member ranges between 0 and 60 degrees. The obstacle member is disposed on the structural wall, and a second angle between the obstacle member and the structural wall is greater than 90 degrees. The present disclosure further provides an assay device including said reaction assay for biochemical test.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: APEX BIOTECHNOLOGY CORP.
    Inventors: Sz Hau Chen, Ming Chang Hsu, Yu-Ju Lu, Chia-Jung Wang, Jui-Pin Hrian