Patents by Inventor Jungwon Suh
Jungwon Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126438Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Inventors: Jungwon Suh, Pankaj Sharadchandra Deshmukh, Michael Hawjing Lo, Subbarao Palacharla, Olivier Alavoine
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Publication number: 20240111424Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: ApplicationFiled: December 4, 2023Publication date: April 4, 2024Inventors: Shyamkumar THOZIYOOR, Pankaj DESHMUKH, Jungwon SUH, Subbarao PALACHARLA
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Publication number: 20240078202Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jungwon SUH, Pankaj DESHMUKH, Shyamkumar THOZIYOOR, Subbarao PALACHARLA
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Patent number: 11907141Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.Type: GrantFiled: September 6, 2022Date of Patent: February 20, 2024Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Pankaj Deshmukh, Shyamkumar Thoziyoor, Subbarao Palacharla
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Patent number: 11893240Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: GrantFiled: October 28, 2021Date of Patent: February 6, 2024Assignee: QUALCOMM IncorporatedInventors: Shyamkumar Thoziyoor, Pankaj Deshmukh, Jungwon Suh, Subbarao Palacharla
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Patent number: 11823762Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.Type: GrantFiled: January 4, 2023Date of Patent: November 21, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Joon Young Park, Mahalingam Nagarajan
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Publication number: 20230305971Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.Type: ApplicationFiled: February 9, 2022Publication date: September 28, 2023Inventors: Pankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla
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Publication number: 20230298682Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Inventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
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Patent number: 11728003Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.Type: GrantFiled: April 30, 2021Date of Patent: August 15, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
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Publication number: 20230170037Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.Type: ApplicationFiled: April 12, 2022Publication date: June 1, 2023Inventor: Jungwon Suh
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Patent number: 11662919Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
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Publication number: 20230154502Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.Type: ApplicationFiled: January 4, 2023Publication date: May 18, 2023Inventors: Jungwon SUH, Joon Young PARK, Mahalingam NAGARAJAN
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Publication number: 20230136996Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Shyamkumar THOZIYOOR, Pankaj DESHMUKH, Jungwon SUH, Subbarao PALACHARLA
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Patent number: 11631450Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: GrantFiled: July 16, 2021Date of Patent: April 18, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
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Patent number: 11551730Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.Type: GrantFiled: January 26, 2021Date of Patent: January 10, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Joon Young Park, Mahalingam Nagarajan
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Publication number: 20220238142Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.Type: ApplicationFiled: January 26, 2021Publication date: July 28, 2022Inventors: Jungwon Suh, Joon Young Park, Mahalingam Nagarajan
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Patent number: 11372717Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.Type: GrantFiled: July 30, 2020Date of Patent: June 28, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
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Patent number: 11360897Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.Type: GrantFiled: April 15, 2021Date of Patent: June 14, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Pankaj Deshmukh, Michael Hawjing Lo, Shyamkumar Thoziyoor
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Patent number: 11295803Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.Type: GrantFiled: July 31, 2020Date of Patent: April 5, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
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Patent number: 11281526Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.Type: GrantFiled: August 31, 2020Date of Patent: March 22, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun, Jungwon Suh