Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support an efficient mode for reducing power consumption in a memory module while maintaining access to all contents of memory. In a first aspect, a method includes communicating, by a memory module, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; communicating second data stored in the second plurality of banks to the host device through a second sub-channel in the first operating mode; receiving a command to enter a second operating mode; and communicating third data stored in the first plurality of banks and fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

Abstract: Various embodiments include systems and methods for improving the efficiency of a memory subsystem in a computing device. The memory subsystem may be configured to detect memory access events and determining their associated timings and determine an efficiency of the memory subsystem based on operational parameters of the memory subsystem, the detecting memory access events, and associated timings. The memory subsystem may adjust the operational parameters of the memory subsystem based on the determined efficiency of the memory subsystem. The memory subsystem may dynamically modify the operations of the memory subsystem based on the adjusted operational parameters.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method includes receiving, from a host, a message comprising instructions to configure a first portion of a memory array for storage of data and metadata and to configure a second portion of the memory array for storage of only data and configuring the memory array in accordance with the received message. Other aspects and features are also claimed and described.

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.