Abstract: A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state.

Abstract: In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

Abstract: Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract: A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank.

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.