Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

Abstract: An electronic device and method utilizes an external sensor group to facilitate miniaturization the device and repair/replacement of external sensors. An interface connected to an external sensor package including at least one sensor. A processor that when the external sensor package is connected through the interface, determines from which group the external sensor package is included in among pre-configured groups and controls the performance of a function corresponding to the determined group.

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state. By reducing the amount of data that is transferred between a host and a memory element, power consumption is reduced.

Abstract: Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information.

Abstract: A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.

Abstract: A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.

Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

Abstract: A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract: A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane.

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

Abstract: An electronic device and method utilizes an external sensor group to facilitate miniaturization the device and repair/replacement of external sensors. An interface connected to an external sensor package including at least one sensor. A processor that when the external sensor package is connected through the interface, determines from which group the external sensor package is included in among pre-configured groups and controls the performance of a function corresponding to the determined group.