Abstract: Disclosed herein are a color filter having a black matrix and an apparatus and method of manufacturing the same. The method may include applying an organic film to a substrate, forming a pattern on the organic film by applying pressure to the organic film with a mold having prominences and depressions, and forming a black matrix by applying an ink to the pattern of the organic film. The formation of the black matrix may be achieved by a roll to roll method. The black matrix is easily formed by carrying out imprinting and printing on the organic film applied to the substrate. The black matrix may have a fine line width of a nano level by imprinting and printing. Further, since the black matrix is formed by the roll to roll method, material costs may be reduced and the color filter may be manufactured at a relatively high speed.

Abstract: Disclosed herein is a roll-to-roll patterning apparatus and a patterning system using the same. The patterning system may include a supply roll to supply a film member, a recovery roll to recover the film member, and a roll-to-roll patterning apparatus forming a coating on the film member. The roll-to-roll patterning apparatus may include a pattern roller, a plurality of press rollers, and an alignment roller. The pattern roller may include an outer peripheral surface with a first pattern. The plurality of press rollers may press a film member against the pattern roller to form a second pattern on the film member. The alignment roller may be spaced apart from the pattern roller and may be arranged at an upstream position in a movement direction of the film member. The alignment roller may align the film member entering a region between the pattern roller and the plurality of press rollers.

Abstract: In forming a pattern on a substrate with reduced pattern error using a mold having an area smaller than an area of the substrate, a first resin pattern is formed on at least a first of a plurality of regions of an etching object layer by imprinting resin applied to the etching object layer using a first mold The etching object layer is then etched using the first resin pattern as an etching mask. A second resin pattern is formed on at least a second of the plurality of regions by imprinting resin applied to the etching object layer using a second mold. The etching object layer is again etched using the second resin pattern as an etching mask.

Abstract: Disclosed is a substrate alignment apparatus capable of performing coarse and fine alignments of a substrate in a progressing route to remove or reduce an alignment error between the substrate and a pattern roll. The coarse alignment may be performed by moving a frame using a stage when the alignment error is relatively large, and the fine alignment may be performed by moving subsidiary rollers of a roller unit relative to a main roller of a roller unit when the alignment error is relatively small. An example substrate alignment apparatus may include a frame and a roller unit rotatably fixed to the frame to support a substrate, wherein the roller unit includes a main roller, and at least one subsidiary roller fixed to the main roller such that the at least one subsidiary roller can move relative to the main roller to align the substrate.

Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.

Abstract: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.

Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.

Abstract: A method of manufacturing thin film transistor and color filter substrates suitable for liquid crystal displays comprises imprinting a pattern in a resin layer formed on a substrate by disposing a mold on the resin layer, aligning the mold and the substrate, curing an edge portion of the resin layer, pressing the full area of the resin layer, curing the full area of the resin layer, and separating the mold from the resin layer.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: Disclosed are agents that inhibit histone deacetylase. More specifically, the present invention relates to novel hydroxamic acid derivatives or pharmaceutically acceptable salts thereof for anticancer agents or other therapeutic agents based on their histone deacetylase inhibitory activity.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: Disclosed are a mask mold, a manufacturing method thereof, and a method for forming a large-sized micro pattern using the manufactured mask mold, in which the size of a nano-level micro pattern can be enlarged using a simple method with low cost and interference and stitching errors between cells forming a large area can be minimized. The method for manufacturing the mask mold includes the operations of coating resist on a mask or a plurality of small molds having an engraved micro pattern, pressing the small molds to imprint the micro pattern on the resist, curing the resist, and releasing the small molds from the resist.

Abstract: This invention relates to Pulsatillae Radix extract for improving brain functions. More specifically, this invention relates to Pulsatillae Radix extract, its active fractions and a pharmaceutical product and a health food containing the same respectively having a protective activity against neurotoxicity and a growth inhibitory effect induced by beta-amyloid, an anti-oxidizing effect, a neuron proliferating effect and improving memory thereby effective in improving brain functions such as Mild Cognitive Impairment and dementia.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.

Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

Abstract: A heater bracket assembly for securing a heater case in a dryer is disclosed. The heater bracket assembly includes a supporting part secured to a bottom end of the heater case for supporting the heater case, a fixing part secured to a base plate of the dryer, and a connecting part connecting the supporting part and the fixing part, wherein the supporting part comprises a first extension member extended therefrom which engages with an aperture provided to the bottom end of the heater case such that the supporting part is initially secured to the heater case.