Patents by Inventor Jung-woo Seo

Jung-woo Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060222966
    Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
    Type: Application
    Filed: January 31, 2006
    Publication date: October 5, 2006
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Patent number: 7098018
    Abstract: The present invention relates to novel aminopeptidase derived from Bacillus licheniformis, a gene encoding the aminopeptidase, an expression vector containing the gene, a cell transformant transfected with the expression vector and a process for preparing a natural type protein using thereof. More particularly, the present invention relates to a gene encoding aminopeptidase which is cloned and manufactured using the recombinant DNA technique, an expression vector containing the gene, a cell transformant transfected with the expression vector and a recombinant aminopeptidase which is necessary to produce recombinant human growth hormone in a natural type protein and can be expressed in a high yield more stably and advantageously, compared with conventional methods for the purification.
    Type: Grant
    Filed: July 6, 2002
    Date of Patent: August 29, 2006
    Assignee: LG Life Sciences Ltd.
    Inventors: Young-Phil Lee, Seung-won Lee, Chul-ho Jung, Hyung-Cheol Kim, Soon-Yong Choi, Jin-suk Kim, Hyun-Sik Kim, Jung-Woo Seo
  • Publication number: 20060186479
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 24, 2006
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Publication number: 20060180843
    Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.
    Type: Application
    Filed: April 4, 2006
    Publication date: August 17, 2006
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20060146595
    Abstract: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
    Type: Application
    Filed: January 6, 2006
    Publication date: July 6, 2006
    Inventors: Jong-Seo Hong, Jung-Woo Seo, Jun-Sik Hong, Jeong-Sic Jeon
  • Publication number: 20060138561
    Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
    Type: Application
    Filed: November 8, 2005
    Publication date: June 29, 2006
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20060134875
    Abstract: A method of forming a storage node of a capacitor includes defining a cell region and a peripheral circuit region in a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate of the cell region and the peripheral circuit region. Buried contact plugs are formed to penetrate the interlayer insulating layer of the cell region. A molding layer is formed on the semiconductor substrate of the cell region and the peripheral circuit region. The molding layer of the cell region is patterned, thereby forming storage node holes exposing the buried contact plugs. A conformal storage node layer is formed on the semiconductor substrate having the storage node holes. A photosensitive layer is formed on the semiconductor substrate having the storage node layer. At this time, the photosensitive layer in the cell region is lower in height than the photosensitive layer in the peripheral circuit region. The semiconductor substrate is exposed using a reticle having a scattering bar.
    Type: Application
    Filed: November 21, 2005
    Publication date: June 22, 2006
    Inventors: Tae-Hyuk Ahn, Jung-Woo Seo
  • Patent number: 7053435
    Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20050233505
    Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
    Type: Application
    Filed: June 16, 2005
    Publication date: October 20, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Tae-hyuk Ahn, Jeong-sic Jeon
  • Patent number: 6927127
    Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 9, 2005
    Assignee: Sasung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Tae-hyuk Ahn, Jeong-sic Jeon
  • Publication number: 20050130983
    Abstract: The invention relates to a series of pyrrolopyrimidinone derivatives, processes for their preparation, intermediates in their preparation, their use as therapeutic agents, and pharmaceutical compositions containing them.
    Type: Application
    Filed: May 2, 2002
    Publication date: June 16, 2005
    Inventors: Dae-Kee Kim, Ju Young Lee, Guang-Jin Im, Jin-Young Choi, Jae-Sun Kim, Je-Ho Ryu, Jae Yoon Jung, JunWon Lee, Tae Kon Kim, Jung-Woo Seo, Hye Young Han, Taek-Soo Kim, Inho Jung
  • Publication number: 20050124679
    Abstract: Disclosed are agents that inhibit histone deacetylase. More specifically, the present invention relates to novel hydroxamic acid derivatives or pharmaceutically acceptable salts thereof for anticancer agents or other therapeutic agents based on their histone deacetylase inhibitory activity.
    Type: Application
    Filed: April 10, 2003
    Publication date: June 9, 2005
    Inventors: Dae-Kee Kim, Ju Young Lee, Nam Kyu Lee, Jae-Sun Kim, Junwon Lee, Suk Ho Lee, Jin Young Choi, Nam Ho Kim, Guang-Jin Im, Tae Kon Kim, Tae Kon Kim, Jung-Woo Seo, Young-Jue Bang
  • Publication number: 20050104110
    Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.
    Type: Application
    Filed: March 10, 2004
    Publication date: May 19, 2005
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20050079673
    Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 14, 2005
    Inventors: Jung-woo Seo, Tae-hyuk Ahn, Jeong-sic Jeon
  • Publication number: 20040253703
    Abstract: The present invention relates to novel aminopeptidase derived from Bacillus licheniformis, a gene encoding the aminopeptidase, an expression vector containing the gene, a cell transformant transfected with the expression vector and a process for preparing a natural type protein using thereof. More particularly, the present invention relates to a gene encoding aminopeptidase which is cloned and manufactured using the recombinant DNA technique, an expression vector containing the gene, a cell transformant transfected with the expression vector and a recombinant aminopeptidase which is necessary to produce recombinant human growth hormone in a natural type protein and can be expressed in a high yield more stably and advantageously, compared with conventional methods for the purification.
    Type: Application
    Filed: December 19, 2003
    Publication date: December 16, 2004
    Inventors: Young-Phil Lee, Seung-won Lee, Chul-ho Jung, Hyung-Cheol Kim, Song-Yong Choi, Jin-Suk Kim, Hyun-Sik Kim, Jung-Woo Seo
  • Publication number: 20040238488
    Abstract: A wafer edge etching apparatus and method for etching an edge of a semiconductor wafer including a bottom electrode, arranged below the semiconductor wafer and acting as a stage to support the semiconductor wafer. A method of etching a semiconductor wafer including inserting a semiconductor wafer into a chamber, increasing a pressure in the chamber, supplying at least one etchant gas to the chamber while further increasing the pressure, supplying power to the chamber and etching the semiconductor wafer at the edge bead or the backside of the semiconductor wafer, discontinuing the power and the etchant gas, venting the chamber with a venting gas, and purging the venting gas from the chamber.
    Type: Application
    Filed: January 23, 2004
    Publication date: December 2, 2004
    Inventors: Chang Won Choi, Jong Baum Kim, Tae Ryong Kim, Jung-Woo Seo, Chang Ju Byun
  • Patent number: 6563098
    Abstract: A high-precision displacement measurement device and linear or rotational displacement measurement method using a unit displacement sensor based on a confocal theory. This device is simpler in construction, lower in cost and superior in resolution to other displacement measurement devices, and is capable of measuring a much wider area than other measurement equipment. The present device is adapted to project a spot of light from a light source on an object whose displacement is to be measured and measure a relative displacement of the object from a displacement of the projected light spot.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: May 13, 2003
    Assignee: Korea Advanced Institute of Technology
    Inventors: Dae Gab Gweon, Jung Woo Seo
  • Publication number: 20020088921
    Abstract: A high-precision displacement measurement device and linear or rotational displacement measurement method using a unit displacement sensor based on a confocal theory. This device is simpler in construction, lower in cost and superior in resolution to other displacement measurement devices, and is capable of measuring a much wider area than other measurement equipment. The present device is adapted to project a spot of light from a light source on an object whose displacement is to be measured and measure a relative displacement of the object from a displacement of the projected light spot.
    Type: Application
    Filed: July 6, 2001
    Publication date: July 11, 2002
    Inventors: Dae Gab Gweon, Jung Woo Seo